On Thu, Aug 29, 2024 at 04:22:35PM -0500, Bjorn Helgaas wrote: > [+cc Richard, Lucas, maintainers of IMX6 PCI] > > On Wed, Aug 28, 2024 at 02:40:33PM -0700, Tim Harvey wrote: > > Greetings, > > > > I have a user that is using an IMX8MM SoC (dwc controller) with a > > miniPCIe card that has a PEX8112 PCI-to-PCIe bridge to a legacy PCI > > device and the device is not getting a valid interrupt. > > Does pci-imx6.c support INTx at all? Yes, dwc controller map INTx message to 4 irq lines, which connect to GIC. we tested it by add nomsi in kernel command line. > > I see that drivers/pci/controller/dwc/pci-imx6.c supports both host > and endpoint modes, but the only mention of "intx" is for an IMX > device in endpoint mode to raise an INTx interrupt. > > A few DWC-based drivers look like they support INTx: > > dra7xx_pcie_init_irq_domain > ks_pcie_config_intx_irq > rockchip_pcie_init_irq_domain (the dwc/pcie-dw-rockchip.c one) > uniphier_pcie_config_intx_irq > > but most (including pci-imx6.c) don't have anything that looks like > those. > > > The PCI bus looks like this: > > 00.00.0: 16c3:abcd (rev 01) > > 01:00.0: 10b5:8112 > > ^^^ PEX8112 x1 Lane PCI bridge > > 02:00.0: 4ddc:1a00 > > 02:01.0: 4ddc:1a00 > > ^^^ PCI devices > > > > lspci -vvv -s 02:00.0: > > 02:00.0 Communication controller: ILC Data Device Corp Device 1a00 (rev 10) > > Subsystem: ILC Data Device Corp Device 1a00 > > Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- > > ParErr- Stepping- SERR- FastB2B- DisINTx- > > Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium > > >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- > > Interrupt: pin A routed to IRQ 0 > > Region 0: Memory at 18100000 (32-bit, non-prefetchable) > > [disabled] [size=256K] > > Region 1: Memory at 18180000 (32-bit, non-prefetchable) > > [disabled] [size=4K] > > ^^^ 'Interrupt: pin A routed to IRQ 0' is wrong look like bridge route PCI bus INTA to msi. I remember msi irq0 is reserved. Do you have more information about bridge's MSI informaiton by lspci? Frank > > > > I found an old thread from 2019 on an NVidia forum [1] where the same > > thing occurred and Nvidia's solution was a patch to the dwc driver to > > call pci_fixup_irqs(): > > diff --git a/drivers/pci/dwc/pcie-designware-host.c > > b/drivers/pci/dwc/pcie-designware-host.c > > index ec2e4a61aa4e..a72ba177a5fd 100644 > > --- a/drivers/pci/dwc/pcie-designware-host.c > > +++ b/drivers/pci/dwc/pcie-designware-host.c > > @@ -477,6 +477,8 @@ int dw_pcie_host_init(struct pcie_port *pp) > > if (pp->ops->scan_bus) > > pp->ops->scan_bus(pp); > > > > + pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); > > + > > pci_bus_size_bridges(bus); > > pci_bus_assign_resources(bus); > > > > Since that time the pci/dwc drivers have changed quite a bit; > > pci_fixup_irqs() was changed to pci_assign_irq() called now from > > pcie_device_probe() and dw_pcie_host_init() calls commit init > > functions. > > > > While I don't have the particular card in hand described above yet to > > test with, I did manage to reproduce this on an imx6dl soc (same dwc > > controller and driver) connected to a TI XIO2001 with an Intel I210 > > behind it and see the exact same issue. > > > > Does anyone understand why legacy PCI interrupt mapping behind a > > bridge isn't working here? > > > > Best regards, > > > > Tim > > [1] https://forums.developer.nvidia.com/t/xavier-not-routing-pci-interrupts-across-pex8112-bridge/78556
