On Wed, 21 Aug 2024, Bjorn Helgaas wrote:
> On Wed, Aug 21, 2024 at 02:02:15PM +0100, daire.mcnamara@xxxxxxxxxxxxx wrote:
> > From: Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx>
> >
> > On Microchip PolarFire SoC (MPFS) the PCIe Root Port can be behind one of
> > three general-purpose Fabric Interface Controller (FIC) buses that
> > encapsulate an AXI-M interface. That FIC is responsible for managing
> > the translations of the upper 32-bits of the AXI-M address. On MPFS,
> > the Root Port driver needs to take account of that outbound address
> > translation done by the parent FIC bus before setting up its own
> > outbound address translation tables. In all cases on MPFS,
> > the remaining outbound address translation tables are 32-bit only.
> >
> > Limit the outbound address translation tables to 32-bit only.
> >
> > This necessitates changing a size_t in mc_pcie_setup_window
> > to a u64 to avoid a compile error on 32-bit platforms.
>
> I don't see this size_t change in this patch. Add "()" after function
> name if there's a relevant function here.
It looks that change was still present in v7 but also "u64" is not correct
either because it was changed to resource_size_t.
> > Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip Polarfire PCIe controller driver")
> > Signed-off-by: Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx>
> > Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> > Reviewed-by: Ilpo Jarvinen <ilpo.jarvinen@xxxxxxxxxxxxxxx>
> > ---
> > .../pci/controller/plda/pcie-microchip-host.c | 30 ++++++++++++++++---
> > 1 file changed, 26 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c
> > index 48f60a04b740..da766de347bd 100644
> > --- a/drivers/pci/controller/plda/pcie-microchip-host.c
> > +++ b/drivers/pci/controller/plda/pcie-microchip-host.c
> > @@ -21,6 +21,8 @@
> > #include "../../pci.h"
> > #include "pcie-plda.h"
> >
> > +#define MC_OUTBOUND_TRANS_TBL_MASK GENMASK(31, 0)
> > +
> > /* PCIe Bridge Phy and Controller Phy offsets */
> > #define MC_PCIE1_BRIDGE_ADDR 0x00008000u
> > #define MC_PCIE1_CTRL_ADDR 0x0000a000u
> > @@ -612,6 +614,27 @@ static void mc_disable_interrupts(struct mc_pcie *port)
> > writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST);
> > }
> >
> > +int mc_pcie_setup_iomems(struct pci_host_bridge *bridge,
> > + struct plda_pcie_rp *port)
> > +{
> > + void __iomem *bridge_base_addr = port->bridge_addr;
> > + struct resource_entry *entry;
> > + u64 pci_addr;
> > + u32 index = 1;
> > +
> > + resource_list_for_each_entry(entry, &bridge->windows) {
> > + if (resource_type(entry->res) == IORESOURCE_MEM) {
> > + pci_addr = entry->res->start - entry->offset;
> > + plda_pcie_setup_window(bridge_base_addr, index,
> > + entry->res->start & MC_OUTBOUND_TRANS_TBL_MASK,
> > + pci_addr, resource_size(entry->res));
> > + index++;
> > + }
> > + }
> > +
> > + return 0;
> > +}
> > +
> > static int mc_platform_init(struct pci_config_window *cfg)
> > {
> > struct device *dev = cfg->parent;
> > @@ -622,15 +645,14 @@ static int mc_platform_init(struct pci_config_window *cfg)
> > int ret;
> >
> > /* Configure address translation table 0 for PCIe config space */
> > - plda_pcie_setup_window(bridge_base_addr, 0, cfg->res.start,
> > - cfg->res.start,
> > - resource_size(&cfg->res));
> > + plda_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & MC_OUTBOUND_TRANS_TBL_MASK,
> > + 0, resource_size(&cfg->res));
> >
> > /* Need some fixups in config space */
> > mc_pcie_enable_msi(port, cfg->win);
> >
> > /* Configure non-config space outbound ranges */
> > - ret = plda_pcie_setup_iomems(bridge, &port->plda);
> > + ret = mc_pcie_setup_iomems(bridge, &port->plda);
> > if (ret)
> > return ret;
> >
> > --
> > 2.34.1
> >
>
--
i.
