On Thu, Aug 15, 2024 at 06:57:25PM -0400, Jim Quinlan wrote:
> The 'type' field used in the driver to discern SoC differences is
> confusing; change it to the more apt 'soc_base'. The 'base' is because
> some SoCs have the same characteristics as previous SoCs so it is
> convenient to classify them in the same group.
>
> Signed-off-by: Jim Quinlan <james.quinlan@xxxxxxxxxxxx>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
- Mani
> ---
> drivers/pci/controller/pcie-brcmstb.c | 42 +++++++++++++--------------
> 1 file changed, 21 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> index d19eeeed623b..26e8f544da4c 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -218,7 +218,7 @@ enum {
> PCIE_INTR2_CPU_BASE,
> };
>
> -enum pcie_type {
> +enum pcie_soc_base {
> GENERIC,
> BCM7425,
> BCM7435,
> @@ -236,7 +236,7 @@ struct inbound_win {
>
> struct pcie_cfg_data {
> const int *offsets;
> - const enum pcie_type type;
> + const enum pcie_soc_base soc_base;
> const bool has_phy;
> u8 num_inbound_wins;
> int (*perst_set)(struct brcm_pcie *pcie, u32 val);
> @@ -277,7 +277,7 @@ struct brcm_pcie {
> u64 msi_target_addr;
> struct brcm_msi *msi;
> const int *reg_offsets;
> - enum pcie_type type;
> + enum pcie_soc_base soc_base;
> struct reset_control *rescal;
> struct reset_control *perst_reset;
> struct reset_control *bridge_reset;
> @@ -295,7 +295,7 @@ struct brcm_pcie {
>
> static inline bool is_bmips(const struct brcm_pcie *pcie)
> {
> - return pcie->type == BCM7435 || pcie->type == BCM7425;
> + return pcie->soc_base == BCM7435 || pcie->soc_base == BCM7425;
> }
>
> /*
> @@ -861,7 +861,7 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie *pcie,
> * security considerations, and is not implemented in our modern
> * SoCs.
> */
> - if (pcie->type != BCM7712)
> + if (pcie->soc_base != BCM7712)
> add_inbound_win(b++, &n, 0, 0, 0);
>
> resource_list_for_each_entry(entry, &bridge->dma_ranges) {
> @@ -878,7 +878,7 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie *pcie,
> * That being said, each BARs size must still be a power of
> * two.
> */
> - if (pcie->type == BCM7712)
> + if (pcie->soc_base == BCM7712)
> add_inbound_win(b++, &n, size, cpu_start, pcie_start);
>
> if (n > pcie->num_inbound_wins)
> @@ -895,7 +895,7 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie *pcie,
> * that enables multiple memory controllers. As such, it can return
> * now w/o doing special configuration.
> */
> - if (pcie->type == BCM7712)
> + if (pcie->soc_base == BCM7712)
> return n;
>
> ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1,
> @@ -1018,7 +1018,7 @@ static void set_inbound_win_registers(struct brcm_pcie *pcie,
> * 7712:
> * All of their BARs need to be set.
> */
> - if (pcie->type == BCM7712) {
> + if (pcie->soc_base == BCM7712) {
> /* BUS remap register settings */
> reg_offset = brcm_ubus_reg_offset(i);
> tmp = lower_32_bits(cpu_addr) & ~0xfff;
> @@ -1046,7 +1046,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> return ret;
>
> /* Ensure that PERST# is asserted; some bootloaders may deassert it. */
> - if (pcie->type == BCM2711) {
> + if (pcie->soc_base == BCM2711) {
> ret = pcie->perst_set(pcie, 1);
> if (ret) {
> pcie->bridge_sw_init_set(pcie, 0);
> @@ -1077,9 +1077,9 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> */
> if (is_bmips(pcie))
> burst = 0x1; /* 256 bytes */
> - else if (pcie->type == BCM2711)
> + else if (pcie->soc_base == BCM2711)
> burst = 0x0; /* 128 bytes */
> - else if (pcie->type == BCM7278)
> + else if (pcie->soc_base == BCM7278)
> burst = 0x3; /* 512 bytes */
> else
> burst = 0x2; /* 512 bytes */
> @@ -1676,7 +1676,7 @@ static const int pcie_offsets_bmips_7425[] = {
>
> static const struct pcie_cfg_data generic_cfg = {
> .offsets = pcie_offsets,
> - .type = GENERIC,
> + .soc_base = GENERIC,
> .perst_set = brcm_pcie_perst_set_generic,
> .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
> .num_inbound_wins = 3,
> @@ -1684,7 +1684,7 @@ static const struct pcie_cfg_data generic_cfg = {
>
> static const struct pcie_cfg_data bcm7425_cfg = {
> .offsets = pcie_offsets_bmips_7425,
> - .type = BCM7425,
> + .soc_base = BCM7425,
> .perst_set = brcm_pcie_perst_set_generic,
> .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
> .num_inbound_wins = 3,
> @@ -1692,7 +1692,7 @@ static const struct pcie_cfg_data bcm7425_cfg = {
>
> static const struct pcie_cfg_data bcm7435_cfg = {
> .offsets = pcie_offsets,
> - .type = BCM7435,
> + .soc_base = BCM7435,
> .perst_set = brcm_pcie_perst_set_generic,
> .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
> .num_inbound_wins = 3,
> @@ -1700,7 +1700,7 @@ static const struct pcie_cfg_data bcm7435_cfg = {
>
> static const struct pcie_cfg_data bcm4908_cfg = {
> .offsets = pcie_offsets,
> - .type = BCM4908,
> + .soc_base = BCM4908,
> .perst_set = brcm_pcie_perst_set_4908,
> .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
> .num_inbound_wins = 3,
> @@ -1716,7 +1716,7 @@ static const int pcie_offset_bcm7278[] = {
>
> static const struct pcie_cfg_data bcm7278_cfg = {
> .offsets = pcie_offset_bcm7278,
> - .type = BCM7278,
> + .soc_base = BCM7278,
> .perst_set = brcm_pcie_perst_set_7278,
> .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278,
> .num_inbound_wins = 3,
> @@ -1724,7 +1724,7 @@ static const struct pcie_cfg_data bcm7278_cfg = {
>
> static const struct pcie_cfg_data bcm2711_cfg = {
> .offsets = pcie_offsets,
> - .type = BCM2711,
> + .soc_base = BCM2711,
> .perst_set = brcm_pcie_perst_set_generic,
> .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
> .num_inbound_wins = 3,
> @@ -1732,7 +1732,7 @@ static const struct pcie_cfg_data bcm2711_cfg = {
>
> static const struct pcie_cfg_data bcm7216_cfg = {
> .offsets = pcie_offset_bcm7278,
> - .type = BCM7278,
> + .soc_base = BCM7278,
> .perst_set = brcm_pcie_perst_set_7278,
> .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278,
> .has_phy = true,
> @@ -1789,7 +1789,7 @@ static int brcm_pcie_probe(struct platform_device *pdev)
> pcie->dev = &pdev->dev;
> pcie->np = np;
> pcie->reg_offsets = data->offsets;
> - pcie->type = data->type;
> + pcie->soc_base = data->soc_base;
> pcie->perst_set = data->perst_set;
> pcie->bridge_sw_init_set = data->bridge_sw_init_set;
> pcie->has_phy = data->has_phy;
> @@ -1867,7 +1867,7 @@ static int brcm_pcie_probe(struct platform_device *pdev)
> goto fail;
>
> pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION);
> - if (pcie->type == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) {
> + if (pcie->soc_base == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) {
> dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n");
> ret = -ENODEV;
> goto fail;
> @@ -1882,7 +1882,7 @@ static int brcm_pcie_probe(struct platform_device *pdev)
> }
> }
>
> - bridge->ops = pcie->type == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops;
> + bridge->ops = pcie->soc_base == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops;
> bridge->sysdata = pcie;
>
> platform_set_drvdata(pdev, pcie);
> --
> 2.17.1
>
--
மணிவண்ணன் சதாசிவம்
