Hi folks,
DWC PCIe driver introduced a default method to check link up for
DWC controller. However, this is broken by test and can't work 100%
reliably. It was first added by commit 1 and fixed by commit 2. Finally
commit 3 moved PHY debug regs to PCIE_PORT_DEBUG1 which checks
cxpl_debug_info[63:32].
Quoted from DWC databook, section 8.2.3 AXI Bridge Initialization,
Clocking and Reset:
"In RC Mode, your AXI application must not generate any MEM or I/O
requests, until the host software has enabled the Memory Space Enable
(MSE), and IO Space Enable (ISE) bits respectively. Your RC application
should not generate CFG requests until it has confirmed that the link is
up by sampling the smlh_link_up and rdlh_link_up outputs."
So the problem is very clear that cxpl_debug_info from DWC core is
missing rdlh_link_up. So reading PCIE_PORT_DEBUG1 and check smlh_link_up
isn't enough. But I don't know what PCIE_PHY_DEBUG_R1 means. Does it
means both of smlh_link_up and rdlh_link_up? If yes, than commit 3
should be removed. Otherwise it was broken already from the beginning
commit 1.
[1]: commit dac29e6c5460 ("PCI: designware: Add default link up check if
sub-driver doesn't override")
[2]: commit 01c076732e82 ("PCI: designware: Check LTSSM training bit
before deciding link is up")
[3]: commit 60ef4b072ba0 ("PCI: dwc: imx6: Share PHY debug register
definitions")
