Based on the files touched, this looks DWC-specific, so the subject
prefix should be "PCI: dwc: ", not the very generic "debugfs".
The "debugfs" part could go later, e.g.,
PCI: dwc: Add RASDES debugfs support
On Tue, Jun 25, 2024 at 03:08:12PM +0530, Shradha Todi wrote:
> Add support to use the RASDES feature of DesignWare PCIe controller
> using debugfs entries.
>
> RASDES is a vendor specific extended PCIe capability which reads the
> current hardware internal state of PCIe device. Following primary
> features are provided to userspace via debugfs:
> - Debug registers
> - Error injection
> - Statistical counters
This looks like great stuff, thanks a lot for implementing this!
I think this debugfs structure and functionality should be documented
somewhere like Documentation/ABI/testing/. This functionality is
likely to be used by userspace tools like perf that will depend on
this ABI. (Oh, sorry, I just saw Jonathan's similar comment, didn't
mean to duplicate it.)
I don't expect other vendors to implement exactly the same
functionality, but we can at least try to use similar structure if
they do.
> +config PCIE_DW_DEBUGFS
> + bool "DWC PCIe debugfs entries"
> + help
> + Enables debugfs entries for the DWC PCIe Controller.
> + These entries make use of the RAS features in the DW
> + controller to help in debug, error injection and statistical
> + counters
> +int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci)
> +{
> + struct device *dev = pci->dev;
> + int ras_cap;
> + struct rasdes_info *dump_info;
> + char dirname[DWC_DEBUGFS_MAX];
> + struct dentry *dir, *rasdes_debug, *rasdes_err_inj;
> + struct dentry *rasdes_event_counter, *rasdes_events;
> + int i;
> + struct rasdes_priv *priv_tmp;
> +
> + ras_cap = dw_pcie_find_vsec_capability(pci, DW_PCIE_RAS_DES_CAP);
Does this look at config space of a DWC Root Port, or is this in a
RCRB or similar?
Bjorn
