On Wed, Jul 17, 2024 at 10:33:16PM +0530, Manivannan Sadhasivam wrote: > Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt > to the host CPU. This interrupt can be used by the device driver to > identify events such as PCIe link specific events, safety events, etc... > > Hence, document it in the binding along with the existing MSI interrupts. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> > --- > Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 10 ++++++---- > 1 file changed, 6 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml > index d8c0afaa4b19..0d68ce073383 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml > @@ -55,11 +55,12 @@ properties: > - const: aggre1 # Aggre NoC PCIe1 AXI clock > > interrupts: > - minItems: 8 > - maxItems: 8 > + minItems: 9 ABI break > + maxItems: 9 > > interrupt-names: > items: > + - const: global ABI break. You can't add a new entry at the beginning of the list. > - const: msi0 > - const: msi1 > - const: msi2 > @@ -142,7 +143,8 @@ examples: > "aggre0", > "aggre1"; > > - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, > @@ -150,7 +152,7 @@ examples: > <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; > - interrupt-names = "msi0", "msi1", "msi2", "msi3", > + interrupt-names = "global", "msi0", "msi1", "msi2", "msi3", > "msi4", "msi5", "msi6", "msi7"; > #interrupt-cells = <1>; > interrupt-map-mask = <0 0 0 0x7>; > > -- > 2.25.1 >
