Add YAML devicetree schemas for Xilinx QDMA Soft IP PCIe Root Port Bridge. Signed-off-by: Thippeswamy Havalige <thippesw@xxxxxxx> --- .../bindings/pci/xlnx,xdma-host.yaml | 41 ++++++++++++++++++- 1 file changed, 39 insertions(+), 2 deletions(-) --- changes in v2 - update dt node label with pcie. --- diff --git a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml index 2f59b3a73dd2..28d9350a7fb4 100644 --- a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml +++ b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml @@ -14,10 +14,21 @@ allOf: properties: compatible: - const: xlnx,xdma-host-3.00 + enum: + - xlnx,xdma-host-3.00 + - xlnx,qdma-host-3.00 reg: - maxItems: 1 + items: + - description: configuration region and XDMA bridge register. + - description: QDMA bridge register. + minItems: 1 + + reg-names: + items: + - const: cfg + - const: breg + minItems: 1 ranges: maxItems: 2 @@ -111,4 +122,30 @@ examples: interrupt-controller; }; }; + + pcie@80000000 { + compatible = "xlnx,qdma-host-3.00"; + reg = <0x0 0x80000000 0x0 0x10000000>, <0x0 0x90000000 0x0 0x10000000>; + reg-names = "cfg", "breg"; + ranges = <0x2000000 0x0 0xa8000000 0x0 0xa8000000 0x0 0x8000000>, + <0x43000000 0x4 0x80000000 0x4 0x80000000 0x0 0x40000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "misc", "msi0", "msi1"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc_0 0>, + <0 0 0 2 &pcie_intc_0 1>, + <0 0 0 3 &pcie_intc_0 2>, + <0 0 0 4 &pcie_intc_0 3>; + pcie_intc_1: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; }; -- 2.25.1