From: Stewart Hildebrand > Sent: 16 July 2024 20:33 > > This series sets the default minimum resource alignment to 4k for memory > BARs. In preparation, it makes an optimization and addresses some corner > cases observed when reallocating BARs. I consider the prepapatory > patches to be prerequisites to changing the default BAR alignment. Should the BARs be page aligned on systems with large pages? At least as an option for hypervisor pass-through and any than can be mmap()ed into userspace. Does any hardware actually have 'silly numbers' of small memory BARs? I have a vague memory of some ethernet controllers having lots of (?) virtual devices that might have separate registers than can be mapped out to a hypervisor. Expanding those to a large page might be problematic - but needed for security. For more normal hardware just ensuring that two separate targets don't share a page while allowing (eg) two 1k BAR to reside in the same 64k page would give some security. Aligning a small MSIX BAR is unlikely to have any effect on the address space utilisation (for PCIe) since the bridge will assign a power of two sized block - with a big pad (useful for generating pcie errors!) David - Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK Registration No: 1397386 (Wales)
