Hi Jim, On 7/3/24 21:02, Jim Quinlan wrote: > Previously, our chips provided three inbound "BARS" with fixed purposes: > the first was for mapping SOC registers, the second was for memory, and the > third was for memory but with the endian swapped. We typically only used > one of these BARs. > > Complicating that BARs usage was the fact that the PCIe HW would do a > baroque internal mapping of system memory, and concatenate the regions of > multiple memory controllers. > > Newer chips such as the 7712 and Cable Modem SOCs have taken a step forward > and now provide multiple inbound BARs. This works in concert with the > dma-ranges property, where each provided range becomes an inbound BAR. > > This commit provides support for these new chips and their multiple > inbound BARs but also keeps the legacy support for the older system. > > Signed-off-by: Jim Quinlan <james.quinlan@xxxxxxxxxxxx> > --- > drivers/pci/controller/pcie-brcmstb.c | 199 +++++++++++++++++++------- > 1 file changed, 150 insertions(+), 49 deletions(-) > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c > index ffb3e8d8fb2a..5f632fdc0052 100644 > --- a/drivers/pci/controller/pcie-brcmstb.c > +++ b/drivers/pci/controller/pcie-brcmstb.c > @@ -75,15 +75,12 @@ > #define PCIE_MEM_WIN0_HI(win) \ > PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8) > > +#define PCIE_BRCM_MAX_RC_BARS 16 > #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c > #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f > > -#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034 > -#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f > -#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 > +#define PCIE_MISC_RC_BAR4_CONFIG_LO 0x40d4 > > -#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c > -#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f > > #define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044 > #define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048 > @@ -130,6 +127,10 @@ > (PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK | \ > PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK) > > +#define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP 0x40ac > +#define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_MASK 0x1 could you use BIT(0) ~Stan
