The 7712 SOC has a bridge reset which can be described in the device tree.
If it is present, use it. Otherwise, continue to use the legacy method to
reset the bridge.
Signed-off-by: Jim Quinlan <james.quinlan@xxxxxxxxxxxx>
---
drivers/pci/controller/pcie-brcmstb.c | 24 +++++++++++++++++++-----
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index c2eb29b886f7..4104c3668fdb 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -265,6 +265,7 @@ struct brcm_pcie {
enum pcie_type type;
struct reset_control *rescal;
struct reset_control *perst_reset;
+ struct reset_control *bridge;
int num_memc;
u64 memc_size[PCIE_BRCM_MAX_MEMC];
u32 hw_rev;
@@ -732,12 +733,19 @@ static void __iomem *brcm7425_pcie_map_bus(struct pci_bus *bus,
static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val)
{
- u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK;
- u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT;
+ if (pcie->bridge) {
+ if (val)
+ reset_control_assert(pcie->bridge);
+ else
+ reset_control_deassert(pcie->bridge);
+ } else {
+ u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK;
+ u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT;
- tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
- tmp = (tmp & ~mask) | ((val << shift) & mask);
- writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
+ tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
+ tmp = (tmp & ~mask) | ((val << shift) & mask);
+ writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
+ }
}
static void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val)
@@ -1635,6 +1643,12 @@ static int brcm_pcie_probe(struct platform_device *pdev)
goto clk_out;
}
+ pcie->bridge = devm_reset_control_get_optional_exclusive(&pdev->dev, "bridge");
+ if (IS_ERR(pcie->bridge)) {
+ ret = PTR_ERR(pcie->bridge);
+ goto clk_out;
+ }
+
ret = brcm_phy_start(pcie);
if (ret) {
reset_control_rearm(pcie->rescal);
--
2.17.1
Attachment:
smime.p7s
Description: S/MIME Cryptographic Signature
