Hi, On 26/06/2024 11:45, Stanimir Varbanov wrote:
This patchset aims to add bare minimum support for bcm2712
in brcmstb PCIe driver needed to support the peripherals from
RP1 south-bridge found in RPi5. In order to support RP1
PCIe endpoint peripherals a new interrupt controller is added.
The interrupt controller supports 64 interrupt sources which
are enough to handle 61 RP1 peripherals.
Patch 1 is adding DT binding schema for the MIP interrupt
controller, patch 2 is adding relevant changes for PCIe
bcm2712 in yaml. Patch 3 adds MIP intterrupt cotroller driver.
Patches 4 and 5 are preparations for adding bcm2712 support in 6.
The last patch updates bcm2712 .dsti by adding pcie DT nodes.
Few concerns about the implementation:
- the connection between MIP interrupt-controller and PCIe RC is
done through BAR1. The PCIe driver is parsing the msi_parent
DT property in order to obtain few private DT properties like
"brcm,msi-pci-addr" and "reg". IMO this looks hackish but I failed
to find something better. Ideas?
- in downstream RPi kernel "ranges" and "dma-ranges" DT properties
are under an axi {} simple-bus node even that PCIe block is on CPU
MMIO bus. I tried to merge axi {} in soc {} and the result could be
seen on the last patch in this series, but I'm still not sure that
it looks good enough.
This series has been functionally tested on OpenSUSE Tumbleweed with
downstream RP1 south-bridge PCIe endpoint driver implementation as
MFD by using ethernet which is part of it.
The series is based on Andrea's "Add minimal boot support for Raspberry Pi 5"
series.
Comments are welcome!
We are just about submitting support for 7712 which is the sister chip of 2712 and requires similar, if not identical types of changes to pcie-brcmstb.c, would you mind reviewing that patch series when it gets posted by Jim in the next few days, and base yours upon that one? It does separate changes in a more atomic and a more reviewer friendly rather than having one big commit modifying pcie-brcmstb.c
Thanks. -- Florian
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