On Fri, Jun 21, 2024 at 04:48:47PM +0200, Lorenzo Bianconi wrote: > Introduce Airoha EN7581 entry in mediatek-gen3 PCIe controller binding > > Signed-off-by: Lorenzo Bianconi <lorenzo@xxxxxxxxxx> > --- > .../bindings/pci/mediatek-pcie-gen3.yaml | 25 +++++++++++++++---- > 1 file changed, 20 insertions(+), 5 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > index 76d742051f73..0f35cf49de63 100644 > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > @@ -53,6 +53,7 @@ properties: > - mediatek,mt8195-pcie > - const: mediatek,mt8192-pcie > - const: mediatek,mt8192-pcie > + - const: airoha,en7581-pcie > > reg: > maxItems: 1 > @@ -76,20 +77,20 @@ properties: > > resets: > minItems: 1 > - maxItems: 2 > + maxItems: 3 > > reset-names: > minItems: 1 > - maxItems: 2 > + maxItems: 3 > items: > - enum: [ phy, mac ] > + enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ] > > clocks: > - minItems: 4 > + minItems: 1 > maxItems: 6 > > clock-names: > - minItems: 4 > + minItems: 1 You've now relaxed the clock requirements for all devices, and permitted an extra reset on the existing platforms. You'll need to add some per-device min/maxItems constraints to solve that. Thanks, Conor. > maxItems: 6 > > assigned-clocks: > @@ -186,6 +187,20 @@ allOf: > - const: tl_26m > - const: peri_26m > - const: top_133m > + - if: > + properties: > + compatible: > + const: airoha,en7581-pcie > + then: > + properties: > + clock-names: > + items: > + - const: sys_ck > + reset-names: > + items: > + - const: phy-lane0 > + - const: phy-lane1 > + - const: phy-lane2 > > unevaluatedProperties: false > > -- > 2.45.2 > >
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