> +
> + dport = port->parent_dport;
> +
> + /*
> + * Create an xarray entry with the key of the upstream
> + * port of the upstream switch.
> + */
> + us_index = (unsigned long)parent_port->uport_dev;
> + us_ctx = xa_load(res_xa, us_index);
> + if (!us_ctx) {
> + struct cxl_perf_ctx *n __free(kfree) =
> + kzalloc(sizeof(*n), GFP_KERNEL);
> +
> + if (!n)
> + return ERR_PTR(-ENOMEM);
> +
> + ptr = xa_store(res_xa, us_index, n, GFP_KERNEL);
> + if (xa_is_err(ptr))
> + return ERR_PTR(xa_err(ptr));
> + us_ctx = no_free_ptr(n);
> + }
> +
> + us_ctx->port = parent_port;
> +
> + /*
> + * Take the min of the downstream aggregated bandwdith and the
bandwidth
> + * GP provided bandwidth if parent is CXL root.
> + */
> + if (*parent_is_root) {
> + cxl_coordinates_combine(us_ctx->coord, ctx->coord, dport->coord);
> + continue;
> + }
> +
> + /* Below is the calculation for another switch upstream */
> + if (!gp_is_root) {
> + /*
> + * If the device isn't an upstream PCIe port, there's something
> + * wrong with the topology.
> + */
> + if (!dev_is_pci(dev))
> + return ERR_PTR(-EINVAL);
> +
> + /* Retrieve the upstream link bandwidth */
> + pdev = to_pci_dev(dev);
> + rc = cxl_pci_get_bandwidth(pdev, coords);
might as well combine these 2 lines and drop the pdev local variable
(which otherwise could have been scoped to this if() block
rc = cxl_pci_get_bandwidth(to_pci_dev(dev), coords);
> + if (rc)
> + return ERR_PTR(-ENXIO);
> +
> + /*
> + * Take the min of downstream bandwidth and the upstream link
> + * bandwidth.
> + */
> + cxl_coordinates_combine(coords, coords, ctx->coord);
> +
> + /*
> + * Take the min of the calculated bandwdith and the upstream
> + * switch SSLBIS bandwidth.
> + */
> + cxl_coordinates_combine(coords, coords, dport->coord);
> +
> + /*
> + * Aggregate the calculated bandwidth common to an upstream
> + * switch.
> + */
> + cxl_bandwidth_add(us_ctx->coord, us_ctx->coord, coords);
> + } else {
> + /*
> + * Aggregate the bandwidth common to an upstream switch.
> + */
> + cxl_bandwidth_add(us_ctx->coord, us_ctx->coord,
> + ctx->coord);
> + }
> + }
> +
> + return_ptr(res_xa);
> +}
> +
> +static void cxl_region_update_access_coordinate(struct cxl_region *cxlr,
> + struct xarray *input_xa)
> +{
> + struct access_coordinate coord[ACCESS_COORDINATE_MAX];
> + struct cxl_perf_ctx *ctx;
> + unsigned long index;
> +
> + memset(coord, 0, sizeof(coord));
> + xa_for_each(input_xa, index, ctx)
> + cxl_bandwidth_add(coord, coord, ctx->coord);
> +
> + for (int i = 0; i < ACCESS_COORDINATE_MAX; i++) {
> + cxlr->coord[i].read_bandwidth = coord[i].read_bandwidth;
> + cxlr->coord[i].write_bandwidth = coord[i].write_bandwidth;
> + }
> +}
> +
> +static void free_perf_xa(struct xarray *xa)
> +{
> + struct cxl_perf_ctx *ctx;
> + unsigned long index;
> +
> + if (!xa)
> + return;
> +
> + xa_for_each(xa, index, ctx)
> + kfree(ctx);
> + xa_destroy(xa);
> + kfree(xa);
> +}
> +
> +/*
> + * cxl_region_shared_upstream_perf_update - Recalculate the access coordinates
> + * @cxl_region: the cxl region to recalculate
> + *
> + * For certain region construction with endpoints behind CXL switches,
> + * there is the possibility of the total bandwdith for all the endpoints
> + * behind a switch being less or more than the switch upstream link. The
> + * algorithm assumes the configuration is a symmetric topology as that
> + * maximizes performance.
> + *
> + * There can be multiple switches under a RP. There can be multiple RPs under
> + * a HB.
> + *
> + * An example hierarchy:
> + *
> + * CFMWS 0
> + * |
> + * _________|_________
> + * | |
> + * ACPI0017-0 ACPI0017-1
> + * GP0/HB0/ACPI0016-0 GP1/HB1/ACPI0016-1
> + * | | | |
> + * RP0 RP1 RP2 RP3
> + * | | | |
> + * SW 0 SW 1 SW 2 SW 3
> + * | | | | | | | |
> + * EP0 EP1 EP2 EP3 EP4 EP5 EP6 EP7
> + *
> + * Computation for the example hierarchy:
> + *
> + * Min (GP0 to CPU BW,
> + * Min(SW 0 Upstream Link to RP0 BW,
> + * Min(SW0SSLBIS for SW0DSP0 (EP0), EP0 DSLBIS, EP0 Upstream Link) +
> + * Min(SW0SSLBIS for SW0DSP1 (EP1), EP1 DSLBIS, EP1 Upstream link)) +
> + * Min(SW 1 Upstream Link to RP1 BW,
> + * Min(SW1SSLBIS for SW1DSP0 (EP2), EP2 DSLBIS, EP2 Upstream Link) +
> + * Min(SW1SSLBIS for SW1DSP1 (EP3), EP3 DSLBIS, EP3 Upstream link))) +
> + * Min (GP1 to CPU BW,
> + * Min(SW 2 Upstream Link to RP2 BW,
> + * Min(SW2SSLBIS for SW2DSP0 (EP4), EP4 DSLBIS, EP4 Upstream Link) +
> + * Min(SW2SSLBIS for SW2DSP1 (EP5), EP5 DSLBIS, EP5 Upstream link)) +
> + * Min(SW 3 Upstream Link to RP3 BW,
> + * Min(SW3SSLBIS for SW3DSP0 (EP6), EP6 DSLBIS, EP6 Upstream Link) +
> + * Min(SW3SSLBIS for SW3DSP1 (EP7), EP7 DSLBIS, EP7 Upstream link))))
> + */
> +void cxl_region_shared_upstream_perf_update(struct cxl_region *cxlr)
> +{
> + struct xarray *usp_xa, *iter_xa, *working_xa;
> + bool is_root;
> + int rc;
> +
> + lockdep_assert_held(&cxl_dpa_rwsem);
> +
> + usp_xa = kzalloc(sizeof(*usp_xa), GFP_KERNEL);
> + if (!usp_xa)
> return;
> +
> + xa_init(usp_xa);
> +
> + /*
> + * Collect aggregated endpoint bandwidth and store the bandwidth in
> + * an xarray indexed by the upstream port of the switch or RP. The
> + * bandwidth is aggregated per switch. Each endpoint consists of the
> + * minimum of bandwidth from DSLBIS from the endpoint CDAT, the endpoint
> + * upstream link bandwidth, and the bandwidth from the SSLBIS of the
> + * switch CDAT for the switch upstream port to the downstream port that's
> + * associated with the endpoint. If the device is directly connected to
> + * a RP, then no SSLBIS is involved.
> + */
> + for (int i = 0; i < cxlr->params.nr_targets; i++) {
> + struct cxl_endpoint_decoder *cxled = cxlr->params.targets[i];
> +
> + rc = cxl_endpoint_gather_coordinates(cxlr, cxled, usp_xa);
> + if (rc) {
> + free_perf_xa(usp_xa);
> + return;
> + }
> }
>
> + iter_xa = usp_xa;
> + usp_xa = NULL;
> + /*
> + * Iterate through the components in the xarray and aggregate any
> + * component that share the same upstream link from the switch.
> + * The iteration takes consideration of multi-level switch
> + * hierarchy.
> + *
> + * When cxl_switch_iterate_coordinates() detect the grandparent
> + * upstream is a cxl root, it aggregates the bandwidth under
> + * the host bridge. A RP does not have SSLBIS nor does it have
> + * upstream PCIe link.
> + *
> + * When cxl_switch_iterate_coordinates() detect the parent upstream
> + * is a cxl root, it takes the min() of the aggregated RP perfs and
> + * the bandwidth from the Generic Port (GP). 'is_root' is set at this
> + * point as well.
> + */
> + do {
> + working_xa = cxl_switch_iterate_coordinates(iter_xa, &is_root);
> + if (IS_ERR(working_xa))
> + goto out;
> + free_perf_xa(iter_xa);
> + iter_xa = working_xa;
> + } while (!is_root);
> +
> + /*
> + * Aggregate the bandwidths in the xarray (for all the HBs) and update
> + * the region bandwidths with the newly calculated bandwidths.
> + */
> + cxl_region_update_access_coordinate(cxlr, iter_xa);
> +
> +out:
> + free_perf_xa(iter_xa);
> +}
