2024年6月18日(火) 19:47 Michael S. Tsirkin <mst@xxxxxxxxxx>:
>
> On Tue, Jun 18, 2024 at 07:40:34PM +0900, Shunsuke Mie wrote:
> > 2024年6月18日(火) 19:33 Michael S. Tsirkin <mst@xxxxxxxxxx>:
> > >
> > > On Tue, Jun 18, 2024 at 07:15:47PM +0900, Shunsuke Mie wrote:
> > > > Thank you for your response.
> > > >
> > > > 2024年6月18日(火) 18:47 Michael S. Tsirkin <mst@xxxxxxxxxx>:
> > > > >
> > > > > On Tue, Jun 18, 2024 at 08:41:09AM +0900, Shunsuke Mie wrote:
> > > > > > Let's clarify the situation.
> > > > > >
> > > > > > The Virtio device and driver are not working properly due to a
> > > > > > combination of the following reasons:
> > > > > >
> > > > > > 1. Regarding VIRTIO_F_ACCESS_PLATFORM:
> > > > > > - The modern spec includes VIRTIO_F_ACCESS_PLATFORM, which allows
> > > > > > Physical DMAC to be used.
> > > > > > - This feature is not available in the legacy spec.
> > > > >
> > > > > ... because legacy drivers don't set it
> > > > >
> > > > > > 2. Regarding Virtio PCIe Capability:
> > > > > > - The modern spec requires Virtio PCIe Capability.
> > > > >
> > > > > It's a PCI capability actually. People have been asking
> > > > > about option to make it a pcie extended capability,
> > > > > but no one did the spec, qemu and driver work, yet.
> > > > >
> > > > > > - In some environments, Virtio PCIe Capability cannot be provided.
> > > > >
> > > > > why not?
> > > > PCIe Endpoint Controller chips are available from several vendors and allow
> > > > software to describe the behavior of PCIe Endpoint functions. However, they
> > > > offer only limited functionality. Specifically, while PCIe bus communication is
> > > > programmable, PCIe Capabilities are fixed and cannot be made to show as
> > > > virtio's.
> > >
> > > Okay. So where could these structures live, if not in pci config?
> > What does "these structures" refer to? PCIe Capabilities? virtio configs?
>
> Virtio uses a bunch of read only structures that look like this:
>
> struct virtio_pci_cap {
>
> ..... [skipped, specific to pci config caps] ...
>
> u8 cfg_type; /* Identifies the structure. */
> u8 bar; /* Where to find it. */
> u8 id; /* Multiple capabilities of the same type */
> u8 padding[2]; /* Pad to full dword. */
> le32 offset; /* Offset within bar. */
> le32 length; /* Length of the structure, in bytes. */
> };
>
>
> The driver uses that to locate parts of device interface it
> later uses.
>
>
> Per spec, they are currently in pci config, you are saying some devices
> can't have this data in pci config - is that right? Where yes?
I understood. The configuration structure is in the space that is
indicated by BAR0.
Follows the instructions in the spec:
```
4.1.4.10 Legacy Interfaces: A Note on PCI Device Layout
Transitional devices MUST present part of configuration registers in a
legacy configuration structure in BAR0 in the first I/O region of the
PCI device, as documented below.
...
```
>
> > > --
> > > MST
> > >
>
