Hi,
On 6/11/24 14:05, Stefan Wahren wrote:
Hi Andrea,
i added Jeremy, because AFAIK he was deeply involved in ACPI
implementation of the RPi 4.
I'm not sure what to add here, the RPi4 work was done as an example of
using firmware standards to boot multiple OSs with a single
boot/firmware interface. Which means ACPI.
Alternatively, the PCIe/SMCCC might be able to make this device look
more regular, by putting everything on separate PCIe functions.
OTOH, I don't think this device is particularly special, except maybe to
the extent that it doubles down on ideas regarded as best left in the
1990's. The kernel documents how to handle these cases with ACPI _ADR().
A PCI device can create the _ADR nodes by injecting an SSDT into the
ACPI namespace via the PCI option ROMs if the platform firmware doesn't
provide them. Should it though? If I were doing it I might be tempted to
configure the root port in early firmware and hide it from the OS,
claiming instead a bunch of platform devices.
IMHO, DT/Linux platforms should probably do something similar to _ADR()
for consistency rather than requiring the EP driver to get involved.
Further, mixing DT's into a possible ACPI platform is really the worst
of both. Even worse if it requires further distro
dracut/initrd/grub/etc one off hacking or polluting the initrd or ESP of
non RPi platforms to handle the overlay.
So, a custom EP/bus driver option solves the problem on linux for both
DT and ACPI implementations if the device type/offsets are hard coded
into it. And presumably if there is a follow on device, it would use
multiple PCIe functions to avoid all these problems, the ones around
securing the platform with an IOMMU, enabling VFIO, and everything else
one gets for "free" with a proper PCIe EP.
PS:
The PCIe/SMCC API could probably make all these devices appear as PCIe
functions avoiding the need for a monolithic bus or DT/ACPI description
to handle it. But that will likely break the second this device is
plugged into something with an SMMU (this platform doesn't have one,
correct?), and of course if would require all the firmware configured
BAR mappings to remain static, which isn't a problem if its presented as
an integrated endpoint. If someone is interested in doing it that way
then we should talk.
Am 11.06.24 um 17:39 schrieb Andrea della Porta:
Hi,
I'm on the verge of reworking the RP1 driver from downstream in order
for it to be
in good shape for upstream inclusion.
RP1 is an MFD chipset that acts as a south-bridge PCIe endpoint
sporting a pletora
of subdevices (i.e. Ethernet, USB host controller, I2C, PWM, etc.)
whose registers
are all reachable starting from an offset from the BAR address.
The main point here is that while the RP1 as an endpoint itself is
discoverable via
usual PCI enumeraiton, the devices it contains are not discoverable
and must be
declared e.g. via the devicetree. This is an RFC about the correct
approach to use
in integrating the driver and registering the subdevices.
I cannot provide much input into the technical discussion, but i would
prefer an approach which works good with DT and ACPI.
Best regards
Stefan
Link:
- [1]:
https://github.com/raspberrypi/linux/blob/rpi-6.6.y/arch/arm/boot/dts/broadcom/rp1.dtsi
- [2]:
https://github.com/raspberrypi/linux/blob/rpi-6.6.y/drivers/mfd/rp1.c
- [3]:
https://lpc.events/event/17/contributions/1421/attachments/1337/2680/LPC2023%20Non-discoverable%20devices%20in%20PCI.pdf
- [4]:
https://lore.kernel.org/lkml/20230419231155.GA899497-robh@xxxxxxxxxx/t/
- [5]: https://lore.kernel.org/lkml/Y862WTT03%2FJxXUG8@xxxxxxxxx/
