RE: [PATCH v8 3/5] PCI: rcar-gen4: Add .ltssm_control() for other SoC support

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Hi Bjorn,

> From: Bjorn Helgaas, Sent: Thursday, June 6, 2024 2:29 AM
> 
> On Mon, May 20, 2024 at 04:42:58PM +0900, Yoshihiro Shimoda wrote:
> > Sequence for controlling the LTSSM state machine is going to change
> > for SoCs like r8a779f0. So let's move the LTSSM code to a new callback
> > ltssm_control() and populate it for each SoCs.
> 
> s/So let's move/Move/
> 
> No need to repost for this, whoever applies it can tweak it.

I need to post v9 patches for Manivannan's feedback, so I'll fix the description on v9.

Best regards,
Yoshihiro Shimoda

> > This also warrants the addition of new compatibles for r8a779g0 and
> > r8a779h0. But since they are already part of the DT binding, it won't
> > make any difference.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> > ---
> >  drivers/pci/controller/dwc/pcie-rcar-gen4.c | 74 ++++++++++++++-------
> >  1 file changed, 50 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > index b11e09505b0b..bcbf0a52890d 100644
> > --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > @@ -48,7 +48,9 @@
> >  #define RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET	0x1000
> >  #define RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET	0x800
> >
> > +struct rcar_gen4_pcie;
> >  struct rcar_gen4_pcie_drvdata {
> > +	int (*ltssm_control)(struct rcar_gen4_pcie *rcar, bool enable);
> >  	enum dw_pcie_device_mode mode;
> >  };
> >
> > @@ -61,27 +63,6 @@ struct rcar_gen4_pcie {
> >  #define to_rcar_gen4_pcie(_dw)	container_of(_dw, struct rcar_gen4_pcie, dw)
> >
> >  /* Common */
> > -static void rcar_gen4_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar,
> > -					bool enable)
> > -{
> > -	u32 val;
> > -
> > -	val = readl(rcar->base + PCIERSTCTRL1);
> > -	if (enable) {
> > -		val |= APP_LTSSM_ENABLE;
> > -		val &= ~APP_HOLD_PHY_RST;
> > -	} else {
> > -		/*
> > -		 * Since the datasheet of R-Car doesn't mention how to assert
> > -		 * the APP_HOLD_PHY_RST, don't assert it again. Otherwise,
> > -		 * hang-up issue happened in the dw_edma_core_off() when
> > -		 * the controller didn't detect a PCI device.
> > -		 */
> > -		val &= ~APP_LTSSM_ENABLE;
> > -	}
> > -	writel(val, rcar->base + PCIERSTCTRL1);
> > -}
> > -
> >  static int rcar_gen4_pcie_link_up(struct dw_pcie *dw)
> >  {
> >  	struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > @@ -127,9 +108,13 @@ static int rcar_gen4_pcie_speed_change(struct dw_pcie *dw)
> >  static int rcar_gen4_pcie_start_link(struct dw_pcie *dw)
> >  {
> >  	struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > -	int i, changes;
> > +	int i, changes, ret;
> >
> > -	rcar_gen4_pcie_ltssm_enable(rcar, true);
> > +	if (rcar->drvdata->ltssm_control) {
> > +		ret = rcar->drvdata->ltssm_control(rcar, true);
> > +		if (ret)
> > +			return ret;
> > +	}
> >
> >  	/*
> >  	 * Require direct speed change with retrying here if the link_gen is
> > @@ -157,7 +142,8 @@ static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw)
> >  {
> >  	struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> >
> > -	rcar_gen4_pcie_ltssm_enable(rcar, false);
> > +	if (rcar->drvdata->ltssm_control)
> > +		rcar->drvdata->ltssm_control(rcar, false);
> >  }
> >
> >  static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
> > @@ -506,6 +492,38 @@ static void rcar_gen4_pcie_remove(struct platform_device *pdev)
> >  	rcar_gen4_pcie_unprepare(rcar);
> >  }
> >
> > +static int r8a779f0_pcie_ltssm_control(struct rcar_gen4_pcie *rcar, bool enable)
> > +{
> > +	u32 val;
> > +
> > +	val = readl(rcar->base + PCIERSTCTRL1);
> > +	if (enable) {
> > +		val |= APP_LTSSM_ENABLE;
> > +		val &= ~APP_HOLD_PHY_RST;
> > +	} else {
> > +		/*
> > +		 * Since the datasheet of R-Car doesn't mention how to assert
> > +		 * the APP_HOLD_PHY_RST, don't assert it again. Otherwise,
> > +		 * hang-up issue happened in the dw_edma_core_off() when
> > +		 * the controller didn't detect a PCI device.
> > +		 */
> > +		val &= ~APP_LTSSM_ENABLE;
> > +	}
> > +	writel(val, rcar->base + PCIERSTCTRL1);
> > +
> > +	return 0;
> > +}
> > +
> > +static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_pcie = {
> > +	.ltssm_control = r8a779f0_pcie_ltssm_control,
> > +	.mode = DW_PCIE_RC_TYPE,
> > +};
> > +
> > +static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_pcie_ep = {
> > +	.ltssm_control = r8a779f0_pcie_ltssm_control,
> > +	.mode = DW_PCIE_EP_TYPE,
> > +};
> > +
> >  static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_pcie = {
> >  	.mode = DW_PCIE_RC_TYPE,
> >  };
> > @@ -515,6 +533,14 @@ static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_pcie_ep = {
> >  };
> >
> >  static const struct of_device_id rcar_gen4_pcie_of_match[] = {
> > +	{
> > +		.compatible = "renesas,r8a779f0-pcie",
> > +		.data = &drvdata_r8a779f0_pcie,
> > +	},
> > +	{
> > +		.compatible = "renesas,r8a779f0-pcie-ep",
> > +		.data = &drvdata_r8a779f0_pcie_ep,
> > +	},
> >  	{
> >  		.compatible = "renesas,rcar-gen4-pcie",
> >  		.data = &drvdata_rcar_gen4_pcie,
> > --
> > 2.25.1
> >





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