On Fri, Jun 07, 2024 at 05:01:56PM -0600, Alex Williamson wrote: > On Fri, 7 Jun 2024 17:33:20 -0500 > Bjorn Helgaas <helgaas@xxxxxxxxxx> wrote: > > > On Tue, May 07, 2024 at 03:31:23PM -0600, Alex Williamson wrote: > > > Resizing BARs can be blocked when a device in the bridge hierarchy > > > itself consumes resources from the resized range. This scenario is > > > common with Intel Arc DG2 GPUs where the following is a typical > > > topology: > > > > > > +-[0000:5d]-+-00.0-[5e-61]----00.0-[5f-61]--+-01.0-[60]----00.0 Intel Corporation DG2 [Arc A380] > > > \-04.0-[61]----00.0 Intel Corporation DG2 Audio Controller > ... > > > pci 0000:60:00.0: BAR 2 [mem 0xbfe0000000-0xbfefffffff 64bit pref]: releasing > > > pcieport 0000:5f:01.0: bridge window [mem 0xbfe0000000-0xbfefffffff 64bit pref]: releasing > > > pci 0000:5e:00.0: bridge window [mem 0xbfe0000000-0xbfefffffff 64bit pref]: releasing > > > pci 0000:5e:00.0: BAR 0 [mem 0xbff0000000-0xbff07fffff 64bit pref]: releasing > > > pcieport 0000:5d:00.0: bridge window [mem 0xbfe0000000-0xbff07fffff 64bit pref]: releasing > > > pcieport 0000:5d:00.0: bridge window [mem 0xb000000000-0xb2ffffffff 64bit pref]: assigned > > > pci 0000:5e:00.0: bridge window [mem 0xb000000000-0xb1ffffffff 64bit pref]: assigned > > > pci 0000:5e:00.0: BAR 0 [mem 0xb200000000-0xb2007fffff 64bit pref]: assigned It didn't occur to me before, but don't we have a potential issue here because we relocated 5e:00.0 BAR 0 from 0xbff0000000 to 0xb200000000 without notifying any code that might be using it? I'm worried about vendor-specific perf/EDAC/etc drivers that can't claim the the bridge using pci_register_driver() because the pcieport driver is in the way. I think some of those drivers go behind the back of the driver model to locate their device and ioremap the BAR direction. Bjorn
