On Wed, May 29, 2024 at 10:29:04AM +0200, Niklas Cassel wrote:
> The PCIe controller in rk3568 and rk3588 can operate in endpoint mode.
> This endpoint mode support heavily leverages the existing code in
> pcie-designware-ep.c.
>
> Add support for endpoint mode to the existing pcie-dw-rockchip glue
> driver.
>
> Signed-off-by: Niklas Cassel <cassel@xxxxxxxxxx>
Couple of comments below. With those addressed,
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> ---
> drivers/pci/controller/dwc/Kconfig | 17 ++-
> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 210 ++++++++++++++++++++++++++
> 2 files changed, 224 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> index 8afacc90c63b..9fae0d977271 100644
> --- a/drivers/pci/controller/dwc/Kconfig
> +++ b/drivers/pci/controller/dwc/Kconfig
> @@ -311,16 +311,27 @@ config PCIE_RCAR_GEN4_EP
> SoCs. To compile this driver as a module, choose M here: the module
> will be called pcie-rcar-gen4.ko. This uses the DesignWare core.
>
> +config PCIE_ROCKCHIP_DW
> + bool
Where is this symbol used?
> +
> config PCIE_ROCKCHIP_DW_HOST
> - bool "Rockchip DesignWare PCIe controller"
> - select PCIE_DW
> + bool "Rockchip DesignWare PCIe controller (host mode)"
> select PCIE_DW_HOST
> depends on PCI_MSI
> depends on ARCH_ROCKCHIP || COMPILE_TEST
> depends on OF
> help
> Enables support for the DesignWare PCIe controller in the
> - Rockchip SoC except RK3399.
> + Rockchip SoC (except RK3399) to work in host mode.
> +
> +config PCIE_ROCKCHIP_DW_EP
> + bool "Rockchip DesignWare PCIe controller (endpoint mode)"
> + select PCIE_DW_EP
> + depends on ARCH_ROCKCHIP || COMPILE_TEST
> + depends on OF
> + help
> + Enables support for the DesignWare PCIe controller in the
> + Rockchip SoC (except RK3399) to work in endpoint mode.
>
> config PCI_EXYNOS
> tristate "Samsung Exynos PCIe controller"
> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> index e133511692af..347721207161 100644
> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
[...]
> +static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg)
> +{
> + struct rockchip_pcie *rockchip = arg;
> + struct dw_pcie *pci = &rockchip->pci;
> + struct device *dev = pci->dev;
> + u32 reg, val;
> +
> + reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC);
> +
> + dev_dbg(dev, "PCIE_CLIENT_INTR_STATUS_MISC: %#x\n", reg);
> + dev_dbg(dev, "LTSSM_STATUS: %#x\n", rockchip_pcie_get_ltssm(rockchip));
> +
> + if (reg & PCIE_LINK_REQ_RST_NOT_INT) {
> + dev_dbg(dev, "hot reset or link-down reset\n");
> + dw_pcie_ep_linkdown(&pci->ep);
> + }
> +
> + if (reg & PCIE_RDLH_LINK_UP_CHGED) {
> + val = rockchip_pcie_get_ltssm(rockchip);
> + if ((val & PCIE_LINKUP) == PCIE_LINKUP) {
> + dev_dbg(dev, "link up\n");
> + dw_pcie_ep_linkup(&pci->ep);
> + }
> + }
> +
> + rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
It is recommended to clear the IRQs at the start of the handler (after status
read).
- Mani
--
மணிவண்ணன் சதாசிவம்
