On Mon, May 20, 2024 at 10:53:56AM -0400, Sean Anderson wrote:
> Add phys properties so Linux can power-on/configure the GTR
> transcievers.
s/transcievers/transceivers/
Possibly s/phys/PHYs/ in subject, commit log, DT description to avoid
confusion with "phys" (short for generic "physical"). Or maybe even
just "PHY properties"?
What does "GTR" mean? Possibly expand that?
> Signed-off-by: Sean Anderson <sean.anderson@xxxxxxxxx>
> ---
>
> Changes in v3:
> - Document phys property
>
> Changes in v2:
> - Remove phy-names
> - Add an example
>
> Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> index 426f90a47f35..cc50795d170b 100644
> --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> @@ -61,6 +61,11 @@ properties:
> interrupt-map:
> maxItems: 4
>
> + phys:
> + minItems: 1
> + maxItems: 4
> + description: One phy per logical lane, in order
> +
> power-domains:
> maxItems: 1
>
> @@ -110,6 +115,7 @@ examples:
> - |
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/phy/phy.h>
> #include <dt-bindings/power/xlnx-zynqmp-power.h>
> soc {
> #address-cells = <2>;
> @@ -138,6 +144,7 @@ examples:
> <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
> <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
> msi-parent = <&nwl_pcie>;
> + phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
> power-domains = <&zynqmp_firmware PD_PCIE>;
> iommus = <&smmu 0x4d0>;
> pcie_intc: legacy-interrupt-controller {
> --
> 2.35.1.1320.gc452695387.dirty
>
