On Thu, 9 May 2024, Jonathan Cameron wrote:
> On Wed, 8 May 2024 16:47:42 +0300
> Ilpo Järvinen <ilpo.jarvinen@xxxxxxxxxxxxxxx> wrote:
>
> > Currently, PCIe Link Speeds are adjusted by custom code rather than in
> > a common function provided in PCI core. PCIe bandwidth controller
> > (bwctrl) introduces an in-kernel API to set PCIe Link Speed. Convert
> > Target Speed quirk to use the new API.
> >
> > The new API is also intended to be used in an upcoming commit that adds
> > a thermal cooling device to throttle PCIe bandwidth when thermal
> > thresholds are reached.
> >
> > The PCIe bandwidth control procedure is as follows. The highest speed
> > supported by the Port and the PCIe device which is not higher than the
> > requested speed is selected and written into the Target Link Speed in
> > the Link Control 2 Register. Then bandwidth controller retrains the
> > PCIe Link.
> >
> > Bandwidth Notifications enable the cur_bus_speed in the struct pci_bus
> > to keep track PCIe Link Speed changes. While Bandwidth Notifications
> > should also be generated when bandwidth controller alters the PCIe Link
> > Speed, a few platforms do not deliver LMBS interrupt after Link
> > Training as expected. Thus, after changing the Link Speed, bandwidth
> > controller makes additional read for the Link Status Register to ensure
> > cur_bus_speed is consistent with the new PCIe Link Speed.
> >
> > Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@xxxxxxxxxxxxxxx>
> > ---
> > drivers/pci/pci.h | 13 ++++
> > drivers/pci/pcie/Makefile | 2 +-
> > drivers/pci/pcie/bwctrl.c | 147 ++++++++++++++++++++++++++++++++++++++
> > drivers/pci/quirks.c | 12 +---
> > include/linux/pci.h | 3 +
> > 5 files changed, 166 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> > index 416540baf27b..324899fbad0a 100644
> > --- a/drivers/pci/pci.h
> > +++ b/drivers/pci/pci.h
> > @@ -270,6 +270,19 @@ void pci_disable_bridge_window(struct pci_dev *dev);
> > struct pci_bus *pci_bus_get(struct pci_bus *bus);
> > void pci_bus_put(struct pci_bus *bus);
> >
> > +#define PCIE_LNKCAP_SLS2SPEED(lnkcap) \
> > +({ \
> > + u32 _lnkcap = (lnkcap) & PCI_EXP_LNKCAP_SLS; \
>
> Why the inconsistency wrt to PCIE_LNKCAP2_SLS2SPEED which doesn't bother with
> this initial mask. It's not needed afterall as the bits checked are all in the
> mask anyway?
>
> I don't really mind which form but they should look the same.
I made it the same as PCIE_LNKCAP2_SLS2SPEED() as it's like you say,
it checks explicit bits so the other bits don't matter.
--
i.
> > + \
> > + (_lnkcap == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
> > + _lnkcap == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
> > + _lnkcap == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
> > + _lnkcap == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
> > + _lnkcap == PCI_EXP_LNKCAP_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
> > + _lnkcap == PCI_EXP_LNKCAP_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
> > + PCI_SPEED_UNKNOWN); \
> > +})
> > +
>
>
>
