On Mon, Dec 18, 2023 at 11:04:29AM +0800, LeoLiu-oc wrote: > From: LeoLiuoc <LeoLiu-oc@xxxxxxxxxxx> > > Define secondary uncorrectable error mask register, secondary > uncorrectable error severity register and secondary error capabilities and > control register bits in AER capability for PCIe to PCI/PCI-X Bridge. > Please refer to PCIe to PCI/PCI-X Bridge Specification, sec 5.2.3.2, > 5.2.3.3 and 5.2.3.4. Please include the spec revision. The only one I'm aware of is r1.0. > Signed-off-by: LeoLiuoc <LeoLiu-oc@xxxxxxxxxxx> > --- > include/uapi/linux/pci_regs.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index a39193213ff2..987c513192e8 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -802,6 +802,9 @@ > #define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ > #define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */ > #define PCI_ERR_ROOT_ERR_SRC 0x34 /* Error Source Identification */ > +#define PCI_ERR_UNCOR_MASK2 0x30 /* PCIe to PCI/PCI-X Bridge */ > +#define PCI_ERR_UNCOR_SEVER2 0x34 /* PCIe to PCI/PCI-X Bridge */ > +#define PCI_ERR_CAP2 0x38 /* PCIe to PCI/PCI-X Bridge */ > > /* Virtual Channel */ > #define PCI_VC_PORT_CAP1 0x04 > -- > 2.34.1 >
