On Fri, Apr 12, 2024 at 11:37:20AM +0900, Damien Le Moal wrote: > The PCIe specifications (PCI Express Electromechanical Specification rev > 2.0, section 2.6.2) mandate that the PERST# signal must remain asserted > for at least 100 usec (Tperst-clk) after the PCIe reference clock > becomes stable (if a reference clock is supplied), and for at least > 100 msec after the power is stable (Tpvperl, defined by the macro > PCIE_T_PVPERL_MS). > > Modify rockchip_pcie_host_init_port() to satisfy these constraints by > adding a sleep period before bringing back PESRT# signal to high using > the ep_gpio GPIO. Since Tperst-clk is the shorter wait time, add an > msleep() call for the longer PCIE_T_PVPERL_MS milliseconds to handle > both timing requirements. > > Signed-off-by: Damien Le Moal <dlemoal@xxxxxxxxxx> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> - Mani > --- > drivers/pci/controller/pcie-rockchip-host.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c > index 300b9dc85ecc..fc868251e570 100644 > --- a/drivers/pci/controller/pcie-rockchip-host.c > +++ b/drivers/pci/controller/pcie-rockchip-host.c > @@ -322,6 +322,7 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip) > rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, > PCIE_CLIENT_CONFIG); > > + msleep(PCIE_T_PVPERL_MS); > gpiod_set_value_cansleep(rockchip->ep_gpio, 1); > > /* 500ms timeout value should be enough for Gen1/2 training */ > -- > 2.44.0 > > -- மணிவண்ணன் சதாசிவம்
