On Wed, Mar 27, 2024 at 1:25 PM Conor Dooley <conor@xxxxxxxxxx> wrote: > > From: Jamie Gibbons <jamie.gibbons@xxxxxxxxxxxxx> > > The GPIO controllers on PolarFire SoC were based on the "soft" IP > CoreGPIO, but the inp/outp registers are at different offsets. Add > compatible to allow for support of both sets of offsets. The soft > core will not always have interrupts wired up, so only enforce them for > the "hard" core on PolarFire SoC. > > Signed-off-by: Jamie Gibbons <jamie.gibbons@xxxxxxxxxxxxx> > Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > --- Applied, thanks! Bart
