The PCI specifications mandate that PERST be asserted for at least 100ms. Make sure that is done in rockchip_pcie_host_init_port() by adding a 100ms sleep before bringing back PESRT signal to high using the ep_gpio GPIO. Comments are also added to clarify this behavior. Signed-off-by: Damien Le Moal <dlemoal@xxxxxxxxxx> --- drivers/pci/controller/pcie-rockchip-host.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c index 300b9dc85ecc..d526b9d26c18 100644 --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c @@ -294,6 +294,7 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip) int err, i = MAX_LANE_NUM; u32 status; + /* Assert PERST */ gpiod_set_value_cansleep(rockchip->ep_gpio, 0); err = rockchip_pcie_init_port(rockchip); @@ -322,6 +323,11 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip) rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, PCIE_CLIENT_CONFIG); + /* + * PCIe specifications mandate that PERST be asserted for at + * least 100ms. + */ + msleep(100); gpiod_set_value_cansleep(rockchip->ep_gpio, 1); /* 500ms timeout value should be enough for Gen1/2 training */ -- 2.44.0
