Any access to GL975x's config space, like `lspci -vv` or pci_save_state(), can still trigger the replay timer timeout error even after commit 015c9cbcf0ad ("mmc: sdhci-pci-gli: GL9750: Mask the replay timer timeout of AER"), albeit with a lower reproduce rate. The AER interrupt can prevent the system from suspending, or can flood the kernel message. So mask the replay timer timeout to resolve the issue. Cc: Victor Shih <victor.shih@xxxxxxxxxxxxxxxxxxx> Cc: Ben Chuang <benchuanggli@xxxxxxxxx> Signed-off-by: Kai-Heng Feng <kai.heng.feng@xxxxxxxxxxxxx> --- drivers/pci/quirks.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index ea476252280a..7ad7141e1c54 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -6223,3 +6223,22 @@ static void pci_fixup_d3cold_delay_1sec(struct pci_dev *pdev) pdev->d3cold_delay = 1000; } DECLARE_PCI_FIXUP_FINAL(0x5555, 0x0004, pci_fixup_d3cold_delay_1sec); + +#ifdef CONFIG_PCIEAER +static void pci_mask_replay_timer_timeout(struct pci_dev *pdev) +{ + struct pci_dev *parent = pci_upstream_bridge(pdev); + u32 val; + + if (!parent || !parent->aer_cap) + return; + + pci_info(pdev, "Mask AER due to hardware defect"); + + pci_read_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, &val); + val |= PCI_ERR_COR_REP_TIMER; + pci_write_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, val); +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout); +#endif -- 2.34.1