Hi Bjorn, Please consider this series for kernel 6.10. The series attempt to add secondary bus reset (SBR) support to CXL. By default, SBR for CXL is masked. Per CXL specification r3.1 8.1.5.2, the Port Control Extensions register bit 0 (Unmask SBR) in the host bridge controls the masking of CXL SBR. "When 0, SBR bit in Bridge Control register of this Port has no effect. When 1, the Port shall generate hot reset when SBR in Bridge Control gets set to 1. Default value of this bit is 0. When the Port is operating in PCIe mode or RCD mode, this field has no effect on SBR functionality and Port shall follow PCIe Base Specification." v2: - Use pci_upstream_bridge() instead of dev->bus->self. (Lukas) - Rename is_cxl_device() to pci_is_cxl(). (Lukas) - Return -ENOTTY on error. (Lukas) Patch 1: Add check to PCI bus_reset path for CXL device and return with error if "Unmask SBR" bit is set to 0. This allows user to realize that SBR is masked for this CXL device. However, if the user sets the "Unmask SBR" bit via a tool such as setpci, then the bus_reset will proceed. Patch2: Add a new PCI reset method "cxl_bus_force" in order to allow the user an intetional way to perform SBR. The code will set the "Unmask SBR" bit to 1 and proceed with bus_reset. The original value of the bit will be restored after the reset operation. Patch3: CXL driver change that provides a ->reset_done() callback. It compares the hardware decoder settings with the existing software configuration and emit warning if they differ. The difference indicates that decoders were programmed before the reset and are now cleared after reset. There may be onlined system memory backed by CXL memory device that are now violently ripped away from kernel mapping. Patch series stemmed from this [1] patch. With comments [2] from Bjorn. [1]: https://lore.kernel.org/linux-cxl/20240215232307.2793530-1-dave.jiang@xxxxxxxxx/ [2]: https://lore.kernel.org/linux-cxl/20240220203956.GA1502351@bhelgaas/
