On Wed, Mar 20, 2024 at 11:45:38AM +0800, Richard Zhu wrote:
> Fix i.MX8MP PCIe EP can't trigger MSI issue.
> There is one 64Kbytes minimal requirement on i.MX8M PCIe outbound
> region configuration.
>
> EP uses Bar0 to set the outboud region to configure the MSI setting.
> Set the page_size to "epc_features->align" to meet the requirement,
> let the MSI can be triggered successfully.
>
> Fixes: 1bd0d43dcf3b ("PCI: imx6: Clean up addr_space retrieval code")
> Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> Reviewed-by: Frank Li <frank.li@xxxxxxx>
> Acked-by: Jason Liu <jason.hui.liu@xxxxxxx>
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 99a60270b26c..3238b63721bc 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -1013,9 +1013,14 @@ static void imx6_pcie_ep_init(struct dw_pcie_ep *ep)
> {
> enum pci_barno bar;
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + const struct pci_epc_features *epc_features;
>
> for (bar = BAR_0; bar <= BAR_5; bar++)
> dw_pcie_ep_reset_bar(pci, bar);
> + if (ep->ops->get_features) {
> + epc_features = ep->ops->get_features(ep);
> + ep->page_size = epc_features->align;
> + }
I suggest in imx6_add_pcie_ep()
ep->page_size = imx_pcie->drvdata->epc_features->aglgin;
it should be set before call dw_pcie_ep_init().
If you like, I can add this fixed to my patch serial to avoid conflict
https://lore.kernel.org/linux-pci/Zfm720fz9NE0fD%2FP@lizhi-Precision-Tower-5810/T/#t
Frank
> }
>
> static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> --
> 2.37.1
>
