On Mon, Feb 19, 2024 at 04:36:10PM -0500, Frank Li wrote:
> On Wed, Feb 14, 2024 at 02:41:44PM -0500, Frank Li wrote:
> > Convert the layerscape-pci PCIe binding document to yaml format.
> >
> > Additionally, changes for the layerscape-pci endpoint part:
> > - Add interrupt name 'pme' restriction for fsl,ls1028a-pcie-ep,
> > fsl,ls1046a-pcie-ep, and fsl,ls1088a-pcie-ep.
> > - Add register name restrictions: 'reg' and 'addr_space'. 'addr_space' is
> > required by snps,dw-pcie-ep.
> > - Add an example.
> >
> > Changes for the layerscape-pci root complex part:
> > - Add required property: 'reg-names', "#address-cells", "#size-cells",
> > 'device_type', 'bus-range', 'ranges', "#interrupt-cells",
> > 'interrupt-map-mask' and 'interrupt-map'.
> > - Interrupt-names requirement split to each compatible string.
> > - Add register name restrictions: 'reg' and 'config'. 'config' is required
> > by snps,dw-pcie.
>
> @conor
> Any comments about this one?
Sorry I missed this - I've been sick the last week and probably
overzealously deleted stuff from my mailbox. I see Rob replied to this
as I was in the process of reading through the patch, so I only left two
minor comments here.
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + pcie_ep1: pcie-ep@3400000 {
Nit: unused label.
> > +allOf:
> > + - $ref: /schemas/pci/pci-bus.yaml#
> > + - if:
> > + properties:
> > + compatible:
> > + enum:
> > + - fsl,lx2160a-pcie
> > + then:
> > + properties:
> > + interrupts:
> > + maxItems: 2
> > + interrupt-names:
> > + items:
> > + - const: pme
> > + - const: aer
> > + - const: intr
You set maxItems to 2 but there are 3 names. That doesn't seem right!
Chers,
Conor.
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