On 15.02.2024 15:51, Kuppuswamy Sathyanarayanan wrote: > > On 2/15/24 2:39 AM, Konrad Dybcio wrote: >> According to [1], msleep should be used for large sleeps, such as the >> 100-ish ms one in this function. Comply with the guide and use it. >> >> [1] https://www.kernel.org/doc/Documentation/timers/timers-howto.txt >> >> Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> >> --- >> Tested on Qualcomm SC8280XP CRD >> --- >> drivers/pci/controller/dwc/pcie-designware.c | 2 +- >> drivers/pci/controller/dwc/pcie-designware.h | 3 +-- >> 2 files changed, 2 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c >> index 250cf7f40b85..abce6afceb91 100644 >> --- a/drivers/pci/controller/dwc/pcie-designware.c >> +++ b/drivers/pci/controller/dwc/pcie-designware.c >> @@ -655,7 +655,7 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci) >> if (dw_pcie_link_up(pci)) >> break; >> >> - usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); >> + msleep(LINK_WAIT_MSLEEP_MAX); >> } >> >> if (retries >= LINK_WAIT_MAX_RETRIES) { >> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h >> index 26dae4837462..3f145d6a8a31 100644 >> --- a/drivers/pci/controller/dwc/pcie-designware.h >> +++ b/drivers/pci/controller/dwc/pcie-designware.h >> @@ -63,8 +63,7 @@ >> >> /* Parameters for the waiting for link up routine */ >> #define LINK_WAIT_MAX_RETRIES 10 >> -#define LINK_WAIT_USLEEP_MIN 90000 >> -#define LINK_WAIT_USLEEP_MAX 100000 >> +#define LINK_WAIT_MSLEEP_MAX 100 > > Since 90 ms is an acceptable value, why not use it? I suppose I can do that indeed.. Usually I go for the safer option when cleaning up old code, but you're right, 90 should be ok (unless somebody has some documentation stating otherwise) Konrad
