On Wed, 27 Dec 2023 14:44:49 +0500 Nikita Proshkin <n.proshkin@xxxxxxxxx> wrote: > PCIe Base Spec Rev 4.0 introduced new extended capability mandatory for all > ports - Lane Margining at the Receiver. This new feature allows to get an > approximation of the Link eye margin diagram by four points. This > information shows how resistant the Link is to external influences and can > be useful for link debugging and presets tuning. > Previously, this information was only available using a hardware debugger. > > Patch series consists of two parts: > > * Patch for lspci to add Margining registers reading. There is not much > information available without issuing any margining commands, but this > info is useful anyway; > * New pcilmr utility. > > Patch series is also posted as PR on pciutils github: > https://github.com/pciutils/pciutils/pull/162 > > Changelog: > > v2: > - Replace packed structures with bitfields for margining registers parsing > with BIT() and MASK() macros; > - Hardware quirks are now based on ports PCI ID instead of /proc/cpuinfo; > - Refer to the PCIe Spec properly; > - Clean up the formatting; > - Move the entire internal interface of the utility into one common header; > - Use pcilib u8/16/... types instead of types from stdint.h; > - Use common.c functions such as die() and xmalloc() as Martin suggested; > - Change utility building to the variant with linking object files > separately instead of building lmr as a library. > > v1: > https://lore.kernel.org/linux-pci/20231208091734.12225-1-n.proshkin@xxxxxxxxx/ Gently pinging Martin. Review v2 patches, please. I would like to hear any requests/suggestions on them. Thanks. Nikita Proshkin
