Hyper DMA (HDMA) is already supported by the dw-edma dmaengine driver. Unlike it's predecessor Embedded DMA (eDMA), HDMA supports only the unrolled mapping format. This patch series is to integrate HDMA with dwc ep driver. Add change to provide a valid base address of the CSRs from the platform driver and also provides read/write channels count from platform driver since there is no standard way to auto detect the number of available read/write channels in a platform and set the mapping format in platform driver for HDMA. This series passes 'struct dw_edma_chip' to irq_vector() as it needs to access that particular structure and fix to get the eDMA/HDMA max channel count. Also move the HDMA max channel definition to edma.h to maintain uniformity with eDMA. Dependency ---------- Depends on: https://lore.kernel.org/dmaengine/20231117-b4-feature_hdma_mainline-v6-0-ebf7aa0e40d7@xxxxxxxxxxx/ https://lore.kernel.org/all/1701432377-16899-1-git-send-email-quic_msarkar@xxxxxxxxxxx/ Manivannan Sadhasivam (4): dmaengine: dw-edma: Pass 'struct dw_edma_chip' to irq_vector() dmaengine: dw-edma: Introduce helpers for getting the eDMA/HDMA max channel count PCI: dwc: Add HDMA support dmaengine: dw-edma: Move HDMA_V0_MAX_NR_CH definition to edma.h Mrinmay Sarkar (2): PCI: qcom-ep: Provide number of read/write channel for HDMA PCI: epf-mhi: Add flag to enable HDMA for SA8775P drivers/dma/dw-edma/dw-edma-core.c | 29 ++++++++++--- drivers/dma/dw-edma/dw-edma-pcie.c | 4 +- drivers/dma/dw-edma/dw-hdma-v0-core.c | 4 +- drivers/dma/dw-edma/dw-hdma-v0-regs.h | 3 +- drivers/pci/controller/dwc/pcie-designware.c | 63 ++++++++++++++++++++++------ drivers/pci/controller/dwc/pcie-qcom-ep.c | 19 ++++++++- drivers/pci/endpoint/functions/pci-epf-mhi.c | 1 + include/linux/dma/edma.h | 18 +++++++- 8 files changed, 115 insertions(+), 26 deletions(-) -- 2.7.4
