On Mon, Jan 08, 2024 at 06:21:30PM -0500, Frank Li wrote:
> Refector the clock handling logic. Add 'clk_names' define in drvdata. Use
> clk_bulk*() api simplify the code.
>
> Signed-off-by: Frank Li <Frank.Li@xxxxxxx>
> ---
One comment below. With that addressed,
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
>
> Notes:
> Change from v7 to v8
> - update comment message
> - using ARRAY_SIZE to count clk_names.
> Change from v6 to v7
> - none
> Change from v4 to v5
> - update commit message
> - direct using clk name list, instead of macro
> - still keep caculate clk list count because sizeof return pre allocated
> array size.
>
> Change from v3 to v4
> - using clk_bulk_*() API
> Change from v1 to v3
> - none
>
> Change from v4 to v5
> - update commit message
> - direct using clk name list, instead of macro
> - still keep caculate clk list count because sizeof return pre allocated
> array size.
>
> Change from v3 to v4
> - using clk_bulk_*() API
> Change from v1 to v3
> - none
>
> drivers/pci/controller/dwc/pci-imx6.c | 144 ++++++++++----------------
> 1 file changed, 54 insertions(+), 90 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 74703362aeec7..4912c6b08ecf8 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
[...]
>
> +static const char * const
> +imx6_3clks_bus_pcie_phy[] = {"pcie_bus", "pcie", "pcie_phy"};
> +static const char * const
> +imx6_3clks_bus_pcie_aux[] = {"pcie_bus", "pcie", "pcie_aux"};
> +static const char * const
> +imx6_4clks_bus_pcie_phy_aux[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"};
> +static const char * const
> +imx6_4clks_bus_pcie_phy_axi[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"};
> +
Use platform names for defining the array. Like,
imx6q_clks[]
imx6sx_clks[]
imx8mq_clks[]
imx8mm_clks[]
and reuse them for other platforms as well. This gives an idea of how the clocks
got inherited from some base platforms.
- Mani
> static const struct imx6_pcie_drvdata drvdata[] = {
> [IMX6Q] = {
> .variant = IMX6Q,
> @@ -1477,6 +1421,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
> .dbi_length = 0x200,
> .gpr = "fsl,imx6q-iomuxc-gpr",
> + .clk_names = imx6_3clks_bus_pcie_phy,
> + .clks_cnt = ARRAY_SIZE(imx6_3clks_bus_pcie_phy),
> },
> [IMX6SX] = {
> .variant = IMX6SX,
> @@ -1484,6 +1430,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
> IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
> .gpr = "fsl,imx6q-iomuxc-gpr",
> + .clk_names = imx6_4clks_bus_pcie_phy_axi,
> + .clks_cnt = ARRAY_SIZE(imx6_4clks_bus_pcie_phy_axi),
> },
> [IMX6QP] = {
> .variant = IMX6QP,
> @@ -1492,40 +1440,56 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
> .dbi_length = 0x200,
> .gpr = "fsl,imx6q-iomuxc-gpr",
> + .clk_names = imx6_3clks_bus_pcie_phy,
> + .clks_cnt = ARRAY_SIZE(imx6_3clks_bus_pcie_phy),
> },
> [IMX7D] = {
> .variant = IMX7D,
> .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
> .gpr = "fsl,imx7d-iomuxc-gpr",
> + .clk_names = imx6_3clks_bus_pcie_phy,
> + .clks_cnt = ARRAY_SIZE(imx6_3clks_bus_pcie_phy),
> },
> [IMX8MQ] = {
> .variant = IMX8MQ,
> .gpr = "fsl,imx8mq-iomuxc-gpr",
> + .clk_names = imx6_4clks_bus_pcie_phy_aux,
> + .clks_cnt = ARRAY_SIZE(imx6_4clks_bus_pcie_phy_aux),
> },
> [IMX8MM] = {
> .variant = IMX8MM,
> .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
> .gpr = "fsl,imx8mm-iomuxc-gpr",
> + .clk_names = imx6_3clks_bus_pcie_aux,
> + .clks_cnt = ARRAY_SIZE(imx6_3clks_bus_pcie_aux),
> },
> [IMX8MP] = {
> .variant = IMX8MP,
> .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
> .gpr = "fsl,imx8mp-iomuxc-gpr",
> + .clk_names = imx6_3clks_bus_pcie_aux,
> + .clks_cnt = ARRAY_SIZE(imx6_3clks_bus_pcie_aux),
> },
> [IMX8MQ_EP] = {
> .variant = IMX8MQ_EP,
> .mode = DW_PCIE_EP_TYPE,
> .gpr = "fsl,imx8mq-iomuxc-gpr",
> + .clk_names = imx6_4clks_bus_pcie_phy_aux,
> + .clks_cnt = ARRAY_SIZE(imx6_4clks_bus_pcie_phy_aux),
> },
> [IMX8MM_EP] = {
> .variant = IMX8MM_EP,
> .mode = DW_PCIE_EP_TYPE,
> .gpr = "fsl,imx8mm-iomuxc-gpr",
> + .clk_names = imx6_3clks_bus_pcie_aux,
> + .clks_cnt = ARRAY_SIZE(imx6_3clks_bus_pcie_aux),
> },
> [IMX8MP_EP] = {
> .variant = IMX8MP_EP,
> .mode = DW_PCIE_EP_TYPE,
> .gpr = "fsl,imx8mp-iomuxc-gpr",
> + .clk_names = imx6_3clks_bus_pcie_aux,
> + .clks_cnt = ARRAY_SIZE(imx6_3clks_bus_pcie_aux),
> },
> };
>
> --
> 2.34.1
>
--
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