On Fri, Dec 15, 2023 at 04:45:07PM +0100, Lukas Wunner wrote: > On Fri, Dec 15, 2023 at 05:37:01PM +0200, Andy Shevchenko wrote: > > On Fri, Dec 15, 2023 at 08:52:10AM +0100, Lukas Wunner wrote: > > > On Thu, Dec 14, 2023 at 06:38:41PM +0200, Andy Shevchenko wrote: > > > > On Tue, Dec 12, 2023 at 08:47:46PM +0900, Shin'ichiro Kawasaki wrote: > > > > > +/* Cache BAR0 of P2SB device from function 0 ot 7 */ > > > > > +#define NR_P2SB_RES_CACHE 8 > > > > > > > > This is fifth or so definition for the same, isn't it a good time to create > > > > a treewide definition in pci.h? > > > > > > This isn't something defined in the PCI spec but rather an x86-specific > > > constant, so should preferrably live somewhere in arch/x86/include/asm/. > > > > I'm not sure I am following both paragraphs. > > > > > If you have a "maximum number of PCI functions per device" constant in mind > > > then include/uapi/linux/pci.h might be a good fit. > > > > This is indeed what I have had in mind, but why is this x86 specific? > > I didn't get... > > If you look at it from the angle that you want to cache the > BAR of function 0 of the P2SB and of up to 7 additional functions, > it's an x86 thing. > > If you look at it from the angle "how many functions can a PCIe > device have (absent ARI)", it's a PCIe thing. > > It depends on the way you look at it. ;) I look here from the PCI specification / similar thing perspective. My angle here is "cache the BAR of function 0 of P2SB and of up to as many as PCI specification dictates the device may have". -- With Best Regards, Andy Shevchenko
