The Qualcomm IPQ5332 PCIe controller instances are based on SNPS core 5.90a with Gen3 Single-lane and Dual-lane support. The Qualcomm IP rev is 1.27.0 and hence using the 1_27_0 ops. Signed-off-by: Praveenkumar I <quic_ipkumar@xxxxxxxxxxx> --- This patch depends on the below series which adds PCIe support in Qualcomm IPQ9574 https://lore.kernel.org/all/20230519090219.15925-1-quic_devipriy@xxxxxxxxxxx/ drivers/pci/controller/dwc/pcie-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 109df587234e..3d54de1a71df 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1642,6 +1642,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 }, { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 }, { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 }, + { .compatible = "qcom,pcie-ipq5332", .data = &cfg_1_27_0 }, { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 }, { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 }, { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 }, -- 2.34.1
