Hello! > PCIe Gen 4 spec introduced new extended capability mandatory for all > ports - Lane Margining at the Receiver. This new feature allows to get an > approximation of the Link eye margin diagram by four points. This > information shows how resistant the Link is to external influences and can > be useful for link debugging and presets tuning. > Previously, this information was only available using a hardware debugger. > > Patch series consists of two parts: > > * Patch for lspci to add Margining registers reading. There is not much > information available without issuing any margining commands, but this > info is useful anyway; > * New pcilmr utility. > > Margining capability assumes the exchange of commands with the device, so > its support was implemented as a separate utility pcilmr. > The pcilmr allows you to test Links and supports all the features provided > by the Margining capability. The utility is written using a pcilib, it is > divided into a library part and a main function with arguments parsing in > the pciutils root dir. > Man page is provided as well. > > Utility compilation and man page preparation are integrated into the > pciutils Makefile, so run make is enough to start testing the utility > (Gen 4/5 device is required though). > Utility was written with Linux in mind and was tested only on this OS. Thanks for your contribution. The utility will need some cleanups, but overall I will be glad to accept it. Have a nice fortnight -- Martin `MJ' Mareš <mj@xxxxxx> http://mj.ucw.cz/ United Computer Wizards, Prague, Czech Republic, Europe, Earth, Universe
