I'm not a hardware person, but this looks like interesting work! On Fri, Dec 08, 2023 at 12:17:34PM +0300, Nikita Proshkin wrote: > +Turn off PCIE Leaky Bucket Feature, Re-Equalization and Link Degradation; s/PCIE/PCIe/ to match other uses here. > +The current Link data rate must be 16.0 GT/s or higher (right now > +utility supports Gen 4 and 5 Links); So far, each major PCIe spec revision has added a single new data rate, but that may not always be true, and the spec always uses terminology like "16.0 GT/s or higher" instead of terms like "Gen 4". So "supports 16.0 GT/s and 32.0 GT/s Links" might be clearer. > +The Gen 5 Specification sets allowed range for Timing Margin from 20%\~UI to 50%\~UI and Usage in the spec itself would be more like "PCIe Base Spec Revision 5.0" since it doesn't use "Gen 5". > +According to spec it's possible for Receiver to margin up to MaxLanes + 1 > +lanes simultaneously, but usually this works bad, so this option is for s/works bad/works poorly/ > +experiments mostly.
