On 2023/11/30 09:43, Ilkka Koskinen wrote: > > On Tue, 21 Nov 2023, Shuai Xue wrote: >> This commit adds the PCIe Performance Monitoring Unit (PMU) driver support >> for T-Head Yitian SoC chip. Yitian is based on the Synopsys PCI Express >> Core controller IP which provides statistics feature. The PMU is a PCIe >> configuration space register block provided by each PCIe Root Port in a >> Vendor-Specific Extended Capability named RAS D.E.S (Debug, Error >> injection, and Statistics). >> >> To facilitate collection of statistics the controller provides the >> following two features for each Root Port: >> >> - one 64-bit counter for Time Based Analysis (RX/TX data throughput and >> time spent in each low-power LTSSM state) and >> - one 32-bit counter for Event Counting (error and non-error events for >> a specified lane) >> >> Note: There is no interrupt for counter overflow. >> >> This driver adds PMU devices for each PCIe Root Port. And the PMU device is >> named based the BDF of Root Port. For example, >> >> 30:03.0 PCI bridge: Device 1ded:8000 (rev 01) >> >> the PMU device name for this Root Port is dwc_rootport_3018. >> >> Example usage of counting PCIe RX TLP data payload (Units of bytes):: >> >> $# perf stat -a -e dwc_rootport_3018/Rx_PCIe_TLP_Data_Payload/ >> >> average RX bandwidth can be calculated like this: >> >> PCIe TX Bandwidth = Rx_PCIe_TLP_Data_Payload / Measure_Time_Window >> >> Signed-off-by: Shuai Xue <xueshuai@xxxxxxxxxxxxxxxxx> >> Reviewed-by: Baolin Wang <baolin.wang@xxxxxxxxxxxxxxxxx> >> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx> >> Reviewed-by: Yicong Yang <yangyicong@xxxxxxxxxxxxx> >> Tested-by: Ilkka Koskinen <ilkka@xxxxxxxxxxxxxxxxxxxxxx> > > Looks good to me and seems to work fine. Thus, > > Reviewed-and-tested-by: Ilkka Koskinen <ilkka@xxxxxxxxxxxxxxxxxxxxxx> > > > You can keep my "Tested-by: ..." in the other patches. > > Cheers, Ilkka Thank you very much :) Cheers Shuai
