On Mon, 6 Nov 2023 08:42:43 +0100
Christoph Hellwig <hch@xxxxxx> wrote:
> > 1. hardware which cannot handle an unaligned base address (presumably
> > because the chip performs a simple OR operation to get the addresses
> > of individual fields);
>
> There's all kinds of weird encodings that discard the low bits.
> For NVMe it's the PRPs (that is actually documented in the NVMe
> spec, so it might be easiest to grasp), but except for a Mellox
> vendor extension this is also how all RDMA memory registrations
> work.
Thanks Christoph! So for NVMe in certain contexts the low
bits of addresses get discarded, but in other contexts the high bits
of addresses get discarded and the low bits need to remain the same
after the bounce (and that's why we need commits 36950f2da1ea ("driver
core: add a min_align_mask) and 1f221a0d0dbf ("swiotlb: respect
min_align_mask").
Does that sound about right?
Regards,
Halil
