On 06/11/2023 07:12, Jian Yang wrote: > From: "jian.yang" <jian.yang@xxxxxxxxxxxx> > > Add new properties to support control power supplies and reset pin of > a downstream component. > > Signed-off-by: jian.yang <jian.yang@xxxxxxxxxxxx> > --- > .../bindings/pci/mediatek-pcie-gen3.yaml | 30 +++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > index 7e8c7a2a5f9b..a4f6b48d57fa 100644 > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > @@ -84,6 +84,26 @@ properties: > items: > enum: [ phy, mac ] > > + vpcie1v8-supply: > + description: > + The regulator phandle that provides 1.8V power from root port to a > + downstream component. > + > + vpcie3v3-supply: > + description: > + The regulator phandle that provides 3.3V power from root port to a > + downstream component. How 3.3V supply can go from root port to downstream? Do you mean that root port is the regulator itself (regulator provider)? Sorry, all these supplies look like hacks - stuffing PCI device properties into the PCI controller node. Best regards, Krzysztof
