From: David Epping > Sent: 31 October 2023 10:58 > > Hello ARM PCIe and especially Intel Altera SOCFPGA maintainers, > > the Intel Altera Cyclone V PCIe Root Complex drivers afaik currently > don’t support sending IO TLPs. > The Root Complex IP Core, seemingly unlike many other ARM Root Complexes, It isn't an ARM root complex ... I didn't think any of the Cyclone V had embedded arm cpu. I know some of the more recent Altera FPGA do, by the Cyclone V is pretty old now - although we are still using them in new cards. (Only as PCIe endpoints though.) > does not offer a memory mapping for the IO address space, but instead relies > on indirect addressing via address and data registers. If you are building the FPGA image then all the logic to convert the memory mapped slave cycles (into the fpga logic) is supplied as verilog source. So you should be able to 'fix' it do generate IO TLP instead of data TLP for certain addresses. (A few years back we had to fix it to correctly process multiple data TLP in response to a single read TLP - not a problem now.) ... > To support an AX99100 endpoint (which requires IO BARs for some of its features) I thought that all recent endpoints were required [1] to work with just memory BARs - even going back to the later PCI versions. So I'm surprised a PCIe endpoint need an IO BAR. David [1] well strongly implied that it was a really good idea :-) - Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK Registration No: 1397386 (Wales)
