Hello Bjorn, On 18/10/23 22:06, Bjorn Helgaas wrote: > [+cc Serge (please cc people who have commented on previous revisions)] Sure, I will do so. > > On Wed, Oct 18, 2023 at 01:20:38PM +0530, Siddharth Vadapalli wrote: ... >> >> Changes since v1: >> - Updated patch subject and commit message. >> - Determined that issue is not with the absence of Link as mentioned in >> v1 patch. Even with Link up and endpoint device connected, if >> ks_pcie_v3_65_add_bus() is invoked and executed, all reads to the >> MSI-X offsets return 0xffffffff when pcieport driver attempts to setup >> AER and PME services. The all Fs return value indicates that the MSI-X >> configuration is failing even if Endpoint device is connected. This is >> because the ks_pcie_v3_65_add_bus() function is not applicable to the >> AM654x SoC which uses DW PCIe IP-core version 4.90a. > > Thanks for verifying that this doesn't actually depend on whether the > link is up. > > I think that means we should be able to get rid of the > ks_pcie_v3_65_add_bus() callback altogether and instead do this along > with the rest of the Root Port init. Yes, I will follow Serge's suggestion of adding a new pci_ops structure for the AM654x SoC which uses the new 4.90a controller. I have described it at: https://lore.kernel.org/r/ba217723-1501-4e72-b143-e0047266ea9a@xxxxxx/ and am summarizing it below: I will add the following: static struct pci_ops ks_pcie_am6_ops = { .map_bus = dw_pcie_own_conf_map_bus, .read = pci_generic_config_read, .write = pci_generic_config_write, }; which shall be used for AM654x SoC I will also modify the contents of ks_pcie_host_init() as follows: if(ks_pcie->is_am6) pp->bridge->ops = &ks_pcie_am6_ops; else pp->bridge->ops = &ks_pcie_ops; which will ensure that the .add_bus() method is no longer applicable to the AM654x SoC, which was the case prior to commit 6ab15b5e7057. I shall post the v3 patch with the above changes and also Cc Serge. -- Regards, Siddharth.
