On 18/10/23 16:12, Serge Semin wrote: > On Tue, Oct 17, 2023 at 09:44:51AM +0530, Siddharth Vadapalli wrote: >> Hello, >> >> On 17/10/23 02:59, Serge Semin wrote: >>> Hi Siddharth >>> >> >> ... >> ... > > Are you really sure that it's 4.90a? Here is what my DW PCIe RC > _v4.90_ HW databook says about the BARs: > > "Base Address Registers (Offset: 0x10-x14) The Synopsys core does not > implement the optional BARs for the RC product. This is based on the > assumption that the RC host probably has registers on some other > internal bus and has knowledge and setup access to these registers > already." > > What you cited resides in the _v5.x_ databooks. It makes my thinking > that in your case the IP-core isn't of 4.90a version. I reviewed the function ks_pcie_v3_65_add_bus() and it appears clear to me now that it is applicable only to 3.65a versions. The IP-core however is 4.90a. I have posted the v2 patch at: https://lore.kernel.org/r/20231018075038.2740534-1-s-vadapalli@xxxxxx/ Also, as pointed out by Ravi on the v2 patch's thread at: https://lore.kernel.org/r/c546f8e9-f6ba-41b8-7dff-4a7921b6705f@xxxxxx/ the culprit turned out to be: 6ab15b5e7057 (PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus) which in the process of converting the .scan_bus() callback to .add_bus(), namely: ks_pcie_v3_65_scan_bus() -> ks_pcie_v3_65_add_bus() It added the .add_bus() method within "struct pci_ops ks_pcie_ops" which is actually shared with the 4.90a controller as well. So an "is_am6" check should have also been added to make it no-op for NON-3.65a controllers. I will be posting the v3 patch implementing the above fix if there is no further feedback on the v2 patch from others. -- Regards, Siddharth.
