[+cc Siddharth, Ravi, Sriramakrishnan] On Wed, Oct 11, 2023 at 04:14:15PM +0900, Yoshihiro Shimoda wrote: > According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode > Rev.5.20a, we should disable two BARs to avoid unnecessary memory > assignment during device enumeration. Otherwise, Renesas R-Car Gen4 > PCIe controllers cannot work correctly in host mode. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx> > --- > drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index a7170fd0e847..56cc7ff6d508 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -737,6 +737,14 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) > u32 val, ctrl, num_ctrls; > int ret; > > + /* > + * According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode > + * Rev.5.20a, we should disable two BARs to avoid unnecessary memory > + * assignment during device enumeration. > + */ > + dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, 0x0); > + dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_1, 0x0); I cc'd Siddharth and others because they are working on a Keystone issue with MSI-X that requires BAR0; see https://lore.kernel.org/r/20231011123451.34827-1-s-vadapalli@xxxxxx I assume any DWC controller that uses MSI-X would require BAR0 or BAR1 for the MSI-X Table. I don't have any of the DWC specs and don't know whether any controllers use MSI-X, so just heads up in case they do. This patch was recently merged and will appear in v6.7. Bjorn
