On Thu, Sep 28, 2023 at 06:58:20PM +0800, Jian Yang wrote:
> From: "jian.yang" <jian.yang@xxxxxxxxxxxx>
>
> Add new properties to support control power supplies and reset pin of
> a downstream component.
>
> Signed-off-by: jian.yang <jian.yang@xxxxxxxxxxxx>
> ---
> .../bindings/pci/mediatek-pcie-gen3.yaml | 25 +++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> index 7e8c7a2a5f9b..32031362db58 100644
> --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> @@ -84,6 +84,26 @@ properties:
> items:
> enum: [ phy, mac ]
>
> + pcie1v8-supply:
> + description:
> + The regulator phandle that provides 1.8V power from root port to a
> + downstream component.
> +
> + pcie3v3-supply:
> + description:
> + The regulator phandle that provides 3.3V power from root port to a
> + downstream component.
> +
> + pcie12v-supply:
> + description:
> + The regulator phandle that provides 12V power from root port to a
> + downstream component.
> +
> + dsc-reset-gpios:
This should be in the downstream component if it is something extra. So
not the root port node, but the next one down.
> + description:
> + The extra reset pin other than PERST# required by a downstream component.
> + maxItems: 1
> +
> clocks:
> minItems: 4
> maxItems: 6
> @@ -238,5 +258,10 @@ examples:
> #interrupt-cells = <1>;
> interrupt-controller;
> };
> +
> + pcie@0 {
Missing 'reg'.
> + device_type = "pci";
> + pcie-3v3-supply = <&pcie3v3_regulator>;
This is in the root port (which is good), but you've defined the schema
to put them in the host bridge node. IOW, these need to go in a PCI
root-port or P2P bridge schema which doesn't yet exist. I have an
inprogress branch for dtschema to split up pci-bus.yaml for that
purpose. Will try to finish it up soon.
Rob
