Hi Chad, On Tue, Sep 19, 2023 at 02:17:29PM +0000, Schroeder, Chad wrote: > After researching the issue, I found the commit that lead system error: > > https://lore.kernel.org/all/da77c92796b99ec568bd070cbe4725074a117038.1673769517.git.lukas@xxxxxxxxx/ > > Specifically, this removal: > > - Drop an unnecessary 1 sec delay from pci_reset_secondary_bus() which > is now performed by pci_bridge_wait_for_secondary_bus(). A static > delay this long is only necessary for Conventional PCI, so modern > PCIe systems benefit from shorter reset times as a side effect. Thanks for the report and sorry for the breakage. This endpoint device only supports Gen1 speed (2.5GT/s) and does not support Data Link Layer Link Active Reporting. I have a suspicion that I neglected to take this case into account in pci_bridge_wait_for_secondary_bus(). To better understand what's going on, could you also provide "lspci -vvv" output of the parent bridge above 0000:65:00.0 (i.e. of the bridge whose secondary bus is 65)? Thanks! Lukas
