On 9/11/23 08:53, sharath.kumar.d.m@xxxxxxxxx wrote:
From: D M Sharath Kumar <sharath.kumar.d.m@xxxxxxxxx> added new callback for 1) read,write to root port configuration registers 2) read,write to endpoint configuration registers 3) root port interrupt handler agilex and newer platforms need to implemant the callback and generic root port driver should work ( without much changes ) , legacy platforms (arria and startix) implement configuration read,write directly in wrapper api _altera_pcie_cfg_read/_altera_pcie_cfg_write changelog v2: saperated into two patches 1.refactored the driver for easily portability to future Altera FPGA platforms 2.added support for "Agilex" FPGA this driver supports PCI RP IP on Agilex FPGA, as these are FPGA its up to the user to add PCI RP or not ( as per his needs). we are not adding the device tree as part of this commit. we are expecting the add device tree changes only if he is adding PCI RP IP in his design changelog v3: incorporate review comments from Bjorn Helgaas
You've sent 6 versions of this patchset in a 3-hour time span, what is going on?
Dinh
