On Mon, Sep 11, 2023 at 03:08:08PM -0500, Bjorn Helgaas wrote: > On Fri, Sep 08, 2023 at 01:40:13PM +0000, D M, Sharath Kumar wrote: > > > -----Original Message----- > > > From: Bjorn Helgaas <helgaas@xxxxxxxxxx> > > > Sent: Friday, September 8, 2023 6:14 PM > > > To: D M, Sharath Kumar <sharath.kumar.d.m@xxxxxxxxx> > > > Cc: lpieralisi@xxxxxxxxxx; kw@xxxxxxxxx; robh@xxxxxxxxxx; > > > bhelgaas@xxxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx; dinguyen@xxxxxxxxxx; > > > linux-kernel@xxxxxxxxxxxxxxx > > > Subject: Re: [PATCH v2 1/2] PCI: altera: refactor driver for supporting new > > > platform > > > > > > On Fri, Sep 08, 2023 at 09:09:34AM +0000, D M, Sharath Kumar wrote: > > > > > -----Original Message----- > > > > > From: Bjorn Helgaas <helgaas@xxxxxxxxxx> ... > > > > > > > > > + int (*ep_read_cfg)(struct altera_pcie *pcie, u8 busno, > > > > > > + unsigned int devfn, int where, int size, u32 *value); > > > > > > + int (*ep_write_cfg)(struct altera_pcie *pcie, u8 busno, > > > > > > + unsigned int devfn, int where, int size, u32 value); > > > > > > > > > > "ep_read_cfg" isn't the ideal name because it suggests "endpoint", > > > > > but it may be either an endpoint or a switch upstream port. The > > > > > rockchip driver uses "other", which isn't super descriptive either but > > > might be better. > > > > > > > > > Ok will change to "nonrp_read_cfg" ? > > > > > > I think the important point is not whether it's a Root Port or not, but whether > > > it's on the root *bus* or not. In other words, I think the driver has to > > > determine whether to generate a Type 0 (targeting something on the root > > > bus) or a Type 1 (targeting something below a > > > bridge) config transaction (see PCI-to-PCI Bridge spec r1.2, sec 3.1.2.1). > > > > > > There can be non-Root Ports on the root bus, so "nonrp" doesn't seem quite > > > right. "Other" would be OK, since that's already used by other drivers. > > > Maybe "type0" and "type1" would be better and would fit well with the > > > root_bus_nr check you use to distinguish them? > > > > Situation is > > Root port configuration space - memory mapped > > I don't quite believe the idea that the access method is based on > whether it's a root port. For one thing, you decide whether to use > the memory-mapped accessor or the indirect accessor based on whether > the read targets the *root bus*, not whether it targets a root port. > And obviously you don't *know* whether the device at a B/D/F address > is a root port until after you read the PCIe type. I see eight copies of "[PATCH v3 0/2]" on the list: https://lore.kernel.org/linux-pci/20230616063313.862996-2-sharath.kumar.d.m@xxxxxxxxx/T/#t The duplication just causes confusion and slows things down. I do think the naming as root port config accessors and endpoint config accessors is fundamentally broken and needs to be fixed. It's not a *functional* issue, but it is important to avoid misleading names. > I think using names similar to other drivers will be helpful. > > These all work on the root bus: > > exynos_pcie_rd_own_conf > meson_pcie_rd_own_conf > rockchip_pcie_rd_own_conf > > These work on non-root buses: > > dw_pcie_rd_other_conf > rockchip_pcie_rd_other_conf > > > Non root port configuration space - indirect access/proprietary access > > Type 0 for devices directly connected to root port > > Type 1 for others > > > > > > > +static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno, > > > > > > + unsigned int devfn, int where, int size, > > > > > > + u32 *value) > > > > > > +{ > > > > > > + if (busno == pcie->root_bus_nr && pcie->pcie_data->ops- > > > > > >rp_read_cfg) > > > > > > + return pcie->pcie_data->ops->rp_read_cfg(pcie, busno, > > > > > devfn, > > > > > > + where, size, value); > > > > > > + > > > > > > + if (pcie->pcie_data->ops->ep_read_cfg) > > > > > > + return pcie->pcie_data->ops->ep_read_cfg(pcie, busno, > > > > > devfn, > > > > > > + where, size, value); > > > > > > + return PCIBIOS_FUNC_NOT_SUPPORTED; }
