On Mon, 11 Sep 2023, srinivas pandruvada wrote: > On Mon, 2023-09-11 at 18:47 +0300, Ilpo Järvinen wrote: > > > > Okay, thanks for the clarification. So the point is to plan for > > adding > > support for Link Width later and currently only support throttling > > Link > > Speed. In any case, the Link Width control seems to be controlled > > using > > a different approach (Link Width change does not require Link > > Retraining). > > > > I don't know either how such 2 dimensioned throttling (Link Speed and > > Link Width) is supposed to be realized using the thermal/cooling > > device > > interface which only provides a single integer as the current state. > > That > > is, whether to provide a single cooling device (with a single integer > > exposed to userspace) or separate cooling device for each dimension? > > > > Perhaps thermal people could provide some insight on this? Is there > > some > > precedent I could take look at? > > Yes. The processor cooling device does similar. 1-3 are reserved for P- > state and and 4-7 for T-states. > > But I don't suggest using such method. This causes confusion and > difficult to change. For example if we increase range of P-state > control, then there is no way to know what is the start point of T- > states. Yes. I understand it would be confusing. > It is best to create to separate cooling devices for BW and link width. Okay. If that's the case, then I see no reason to add the Link Width cooling device now as it could do nothing besides reporting the current link width. The only question that then remains is how to take this into account in the naming of the cooling devices, currently PCIe_Port_<pci_name()> is used but perhaps it would be better to change that to PCIe_Port_Link_Speed_... to allow PCI_Port_Link_Width_... to be added later beside it? > Also there is a requirement that anything you add to thermal sysfs, it > should have some purpose for thermal control. I hope Link width control > is targeted to similar use case BW control. Ability to control Link Width seems to be part of PCIe 6.0 L0p. AFAICT, the reasons are to lower/control power consumption so it seems to be within scope. -- i.
