PCIe1 instance on J7AHP EVM EP connector has reference clock connection
from serdes unlike PCIe0 for which reference clock connection is from
on-board clock generator. To enable PCIe1 instance, ACSPCIE clock buffer
pads have to be enabled to get reference clock output available to PCIe1 EP
This enables clock source select and ACSPCIE clock buffer pads.
Achal Verma (2):
dt-bindings: PCI: ti,j721e-pci-*: Add "ti,syscon-pcie-refclk-out"
property
pci: j721e: Enable reference clock output from serdes
.../bindings/pci/ti,j721e-pci-host.yaml | 53 ++++++++++
.../pci/controller/cadence/pci-j721e-host.c | 96 +++++++++++++++++++
2 files changed, 149 insertions(+)
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2.25.1
