Our controller is expecting ECAM size to be programmed by software. By programming "NWL_ECAM_VALUE_DEFAULT 12" controller can access up to 16MB ECAM region which is used to detect 16 buses, so by updating "NWL_ECAM_VALUE_DEFAULT" to 16 so that controller can access up to 256MB ECAM region to detect 256 buses. Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@xxxxxxx> Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xxxxxxx> --- changes in v3: - Remove unnecessary period at end of subject line. changes in v2: - Update this changes in a seperate patch. --- drivers/pci/controller/pcie-xilinx-nwl.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index d8a3a08be1d5..b51501921d3b 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -126,7 +126,7 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define NWL_ECAM_VALUE_DEFAULT 12 +#define NWL_ECAM_VALUE_DEFAULT 16 #define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_PCIE_CACHE GENMASK(7, 0) @@ -165,7 +165,6 @@ struct nwl_pcie { u32 ecam_size; int irq_intx; int irq_misc; - u32 ecam_value; struct nwl_msi msi; struct irq_domain *legacy_irq_domain; struct clk *clk; @@ -674,7 +673,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) E_ECAM_CR_ENABLE, E_ECAM_CONTROL); nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | - (pcie->ecam_value << E_ECAM_SIZE_SHIFT), + (NWL_ECAM_VALUE_DEFAULT << E_ECAM_SIZE_SHIFT), E_ECAM_CONTROL); nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), @@ -782,7 +781,6 @@ static int nwl_pcie_probe(struct platform_device *pdev) pcie = pci_host_bridge_priv(bridge); pcie->dev = dev; - pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; err = nwl_pcie_parse_dt(pcie, pdev); if (err) { -- 2.17.1